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amd-drm-next-6.20-2026-02-13:

Browse Source 
amdgpu:
 - SMU 13.x fixes
 - DC resume lag fix
 - MPO fixes
 - DCN 3.6 fix
 - VSDB fixes
 - HWSS clean up
 - Replay fixes
 - DCE cursor fixes
 - DCN 3.5 SR DDR5 latency fixes
 - HPD fixes
 - Error path unwind fixes
 - SMU13/14 mode1 reset fixes
 - PSP 15 updates
 - SMU 15 updates
 - RAS fixes
 - Sync fix in amdgpu_dma_buf_move_notify()
 - HAINAN fix
 - PSP 13.x fix
 - GPUVM locking fix
 
 amdkfd:
 - APU GTT as VRAM fix
 
 radeon:
 - HAINAN fix
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Merge tag 'amd-drm-next-6.20-2026-02-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.20-2026-02-13:

amdgpu:
- SMU 13.x fixes
- DC resume lag fix
- MPO fixes
- DCN 3.6 fix
- VSDB fixes
- HWSS clean up
- Replay fixes
- DCE cursor fixes
- DCN 3.5 SR DDR5 latency fixes
- HPD fixes
- Error path unwind fixes
- SMU13/14 mode1 reset fixes
- PSP 15 updates
- SMU 15 updates
- RAS fixes
- Sync fix in amdgpu_dma_buf_move_notify()
- HAINAN fix
- PSP 13.x fix
- GPUVM locking fix

amdkfd:
- APU GTT as VRAM fix

radeon:
- HAINAN fix

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260213220825.1454189-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2026-02-18 12:37:11 +10:00
commit 3e2138510b
91 changed files with 606 additions and 384 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
View File

@ -878,6 +878,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
struct amdgpu_bo *bo[2] = {NULL, NULL};
struct amdgpu_bo_va *bo_va;
bool same_hive = false;
struct drm_exec exec;
int i, ret;
if (!va) {
@ -958,19 +959,25 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
goto unwind;
}
/* Add BO to VM internal data structures */
ret = amdgpu_bo_reserve(bo[i], false);
if (ret) {
pr_debug("Unable to reserve BO during memory attach");
goto unwind;
drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
drm_exec_until_all_locked(&exec) {
ret = amdgpu_vm_lock_pd(vm, &exec, 0);
drm_exec_retry_on_contention(&exec);
if (unlikely(ret))
goto unwind;
ret = drm_exec_lock_obj(&exec, &bo[i]->tbo.base);
drm_exec_retry_on_contention(&exec);
if (unlikely(ret))
goto unwind;
}
bo_va = amdgpu_vm_bo_find(vm, bo[i]);
if (!bo_va)
bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
else
++bo_va->ref_count;
attachment[i]->bo_va = bo_va;
amdgpu_bo_unreserve(bo[i]);
drm_exec_fini(&exec);
if (unlikely(!attachment[i]->bo_va)) {
ret = -ENOMEM;
pr_err("Failed to add BO object to VM. ret == %d\n",

3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -4652,9 +4652,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
dev_info(adev->dev, "Pending hive reset.\n");
amdgpu_set_init_level(adev,
AMDGPU_INIT_LEVEL_MINIMAL_XGMI);
} else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
!amdgpu_device_has_display_hardware(adev)) {
r = psp_gpu_reset(adev);
} else {
tmp = amdgpu_reset_method;
/* It should do a default reset when loading or reloading the driver,

5
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -2164,6 +2164,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 11):
case IP_VERSION(13, 0, 12):
case IP_VERSION(13, 0, 14):
case IP_VERSION(13, 0, 15):
case IP_VERSION(14, 0, 0):
case IP_VERSION(14, 0, 1):
case IP_VERSION(14, 0, 4):
@ -2988,9 +2989,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 1):
case IP_VERSION(11, 5, 2):
case IP_VERSION(11, 5, 3):
case IP_VERSION(11, 5, 4):
adev->family = AMDGPU_FAMILY_GC_11_5_0;
break;
case IP_VERSION(11, 5, 4):
adev->family = AMDGPU_FAMILY_GC_11_5_4;
break;
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
case IP_VERSION(12, 1, 0):

9
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
View File

@ -514,8 +514,15 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
r = dma_resv_reserve_fences(resv, 2);
if (!r)
r = amdgpu_vm_clear_freed(adev, vm, NULL);
/* Don't pass 'ticket' to amdgpu_vm_handle_moved: we want the clear=true
* path to be used otherwise we might update the PT of another process
* while it's using the BO.
* With clear=true, amdgpu_vm_bo_update will sync to command submission
* from the same VM.
*/
if (!r)
r = amdgpu_vm_handle_moved(adev, vm, ticket);
r = amdgpu_vm_handle_moved(adev, vm, NULL);
if (r && r != -EBUSY)
DRM_ERROR("Failed to invalidate VM page tables (%d))\n",

22
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
View File

@ -232,6 +232,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,
struct amdgpu_vm *vm = &fpriv->vm;
struct amdgpu_bo_va *bo_va;
struct mm_struct *mm;
struct drm_exec exec;
int r;
mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
@ -242,9 +243,18 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,
!amdgpu_vm_is_bo_always_valid(vm, abo))
return -EPERM;
r = amdgpu_bo_reserve(abo, false);
if (r)
return r;
drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
drm_exec_until_all_locked(&exec) {
r = drm_exec_prepare_obj(&exec, &abo->tbo.base, 1);
drm_exec_retry_on_contention(&exec);
if (unlikely(r))
goto out_unlock;
r = amdgpu_vm_lock_pd(vm, &exec, 0);
drm_exec_retry_on_contention(&exec);
if (unlikely(r))
goto out_unlock;
}
amdgpu_vm_bo_update_shared(abo);
bo_va = amdgpu_vm_bo_find(vm, abo);
@ -260,8 +270,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,
amdgpu_bo_unreserve(abo);
return r;
}
amdgpu_bo_unreserve(abo);
drm_exec_fini(&exec);
/* Validate and add eviction fence to DMABuf imports with dynamic
* attachment in compute VMs. Re-validation will be done by
@ -294,7 +303,10 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,
}
}
mutex_unlock(&vm->process_info->lock);
return r;
out_unlock:
drm_exec_fini(&exec);
return r;
}

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
View File

@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
r = amdgpu_vm_flush(ring, job, need_pipe_sync);
if (r) {
amdgpu_ring_undo(ring);
return r;
goto free_fence;
}
}

10
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -1445,6 +1445,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
{
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_fpriv *fpriv;
struct drm_exec exec;
int r, pasid;
/* Ensure IB tests are run on ring */
@ -1484,7 +1485,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
if (r)
goto error_pasid;
drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
drm_exec_until_all_locked(&exec) {
r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0);
drm_exec_retry_on_contention(&exec);
if (unlikely(r))
goto error_vm;
}
fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
drm_exec_fini(&exec);
if (!fpriv->prt_va) {
r = -ENOMEM;
goto error_vm;

7
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -148,6 +148,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp)
break;
case IP_VERSION(13, 0, 6):
case IP_VERSION(13, 0, 14):
case IP_VERSION(13, 0, 15):
ret = psp_init_cap_microcode(psp, ucode_prefix);
ret &= psp_init_ta_microcode(psp, ucode_prefix);
break;
@ -219,6 +220,7 @@ static int psp_early_init(struct amdgpu_ip_block *ip_block)
psp->autoload_supported = false;
break;
case IP_VERSION(13, 0, 12):
case IP_VERSION(13, 0, 15):
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = false;
adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
@ -383,7 +385,8 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))
return false;
db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
@ -735,7 +738,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
ras_intr = amdgpu_ras_intr_triggered();
if (ras_intr)
break;
usleep_range(10, 100);
usleep_range(60, 100);
amdgpu_device_invalidate_hdp(psp->adev, NULL);
}

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
View File

@ -1701,10 +1701,12 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control)
}
res = __verify_ras_table_checksum(control);
if (res)
if (res) {
dev_err(adev->dev,
"RAS table incorrect checksum or error:%d\n",
res);
return -EINVAL;
}
/* Warn if we are at 90% of the threshold or above
*/

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View File

@ -1735,6 +1735,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
{
struct amdgpu_bo_va *bo_va;
amdgpu_vm_assert_locked(vm);
bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
if (bo_va == NULL) {
return NULL;

6
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
View File

@ -42,8 +42,6 @@
#define XGMI_STATE_DISABLE 0xD1
#define XGMI_STATE_LS0 0x81
#define XGMI_LINK_ACTIVE 1
#define XGMI_LINK_INACTIVE 0
static DEFINE_MUTEX(xgmi_mutex);
@ -365,9 +363,9 @@ int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num)
return -ENOLINK;
if ((xgmi_state_reg_val & 0xFF) == XGMI_STATE_LS0)
return XGMI_LINK_ACTIVE;
return AMDGPU_XGMI_LINK_ACTIVE;
return XGMI_LINK_INACTIVE;
return AMDGPU_XGMI_LINK_INACTIVE;
}
/**

15
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
View File

@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_15_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_15_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
@ -121,6 +123,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
case IP_VERSION(13, 0, 10):
case IP_VERSION(13, 0, 12):
case IP_VERSION(13, 0, 14):
case IP_VERSION(13, 0, 15):
err = psp_init_sos_microcode(psp, ucode_prefix);
if (err)
return err;
@ -156,7 +159,8 @@ static void psp_v13_0_bootloader_print_status(struct psp_context *psp,
if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) {
at = 0;
for_each_inst(i, adev->aid_mask) {
bl_status_reg =
@ -202,7 +206,8 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
retry_cnt =
((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))) ?
PSP_VMBX_POLLING_LIMIT :
10;
/* Wait for bootloader to signify that it is ready having bit 31 of
@ -232,7 +237,8 @@ static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) {
ret = psp_v13_0_wait_for_vmbx_ready(psp);
if (ret)
amdgpu_ras_query_boot_status(adev, 4);
@ -872,7 +878,8 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &&
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) &&
(!(adev->flags & AMD_IS_APU))) {
reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));

4
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
View File

@ -45,6 +45,10 @@ static int psp_v15_0_0_init_microcode(struct psp_context *psp)
if (err)
return err;
err = psp_init_ta_microcode(psp, ucode_prefix);
if (err)
return err;
return 0;
}

3
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -1478,7 +1478,8 @@ static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block,
if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &&
(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) &&
(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {
(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) &&
(amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 15))) {
/* AMD_CG_SUPPORT_DRM_MGCG */
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
if (!(data & 0x01000000))

24
drivers/gpu/drm/amd/amdgpu/soc21.c
View File

@ -422,6 +422,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
case IP_VERSION(14, 0, 1):
case IP_VERSION(14, 0, 4):
case IP_VERSION(14, 0, 5):
case IP_VERSION(15, 0, 0):
return AMD_RESET_METHOD_MODE2;
default:
if (amdgpu_dpm_is_baco_supported(adev))
@ -838,9 +839,28 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
break;
case IP_VERSION(11, 5, 4):
adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
AMD_CG_SUPPORT_JPEG_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_FGCG |
AMD_CG_SUPPORT_REPEATER_FGCG |
AMD_CG_SUPPORT_GFX_PERF_CLK |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_DS |
AMD_CG_SUPPORT_HDP_SD |
AMD_CG_SUPPORT_ATHUB_MGCG |
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_IH_CG |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_JPEG;
AMD_PG_SUPPORT_JPEG |
AMD_PG_SUPPORT_GFX_PG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
default:

20
drivers/gpu/drm/amd/amdkfd/kfd_debug.c
View File

@ -404,27 +404,25 @@ static int kfd_dbg_get_dev_watch_id(struct kfd_process_device *pdd, int *watch_i
return -ENOMEM;
}
static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, int watch_id)
static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id)
{
spin_lock(&pdd->dev->watch_points_lock);
/* process owns device watch point so safe to clear */
if ((pdd->alloc_watch_ids >> watch_id) & 0x1) {
pdd->alloc_watch_ids &= ~(0x1 << watch_id);
pdd->dev->alloc_watch_ids &= ~(0x1 << watch_id);
if (pdd->alloc_watch_ids & BIT(watch_id)) {
pdd->alloc_watch_ids &= ~BIT(watch_id);
pdd->dev->alloc_watch_ids &= ~BIT(watch_id);
}
spin_unlock(&pdd->dev->watch_points_lock);
}
static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, int watch_id)
static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id)
{
bool owns_watch_id = false;
spin_lock(&pdd->dev->watch_points_lock);
owns_watch_id = watch_id < MAX_WATCH_ADDRESSES &&
((pdd->alloc_watch_ids >> watch_id) & 0x1);
owns_watch_id = pdd->alloc_watch_ids & BIT(watch_id);
spin_unlock(&pdd->dev->watch_points_lock);
return owns_watch_id;
@ -435,6 +433,9 @@ int kfd_dbg_trap_clear_dev_address_watch(struct kfd_process_device *pdd,
{
int r;
if (watch_id >= MAX_WATCH_ADDRESSES)
return -EINVAL;
if (!kfd_dbg_owns_dev_watch_id(pdd, watch_id))
return -EINVAL;
@ -472,6 +473,9 @@ int kfd_dbg_trap_set_dev_address_watch(struct kfd_process_device *pdd,
if (r)
return r;
if (*watch_id >= MAX_WATCH_ADDRESSES)
return -EINVAL;
if (!pdd->dev->kfd->shared_resources.enable_mes) {
r = debug_lock_and_unmap(pdd->dev->dqm);
if (r) {

3
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
View File

@ -111,6 +111,9 @@ static void set_priority(struct v9_mqd *m, struct queue_properties *q)
static bool mqd_on_vram(struct amdgpu_device *adev)
{
if (adev->apu_prefer_gtt)
return false;
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(9, 4, 3):
case IP_VERSION(9, 5, 0):

27
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -3479,7 +3479,17 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
struct dc_commit_streams_params commit_params = {};
if (dm->dc->caps.ips_support) {
if (!amdgpu_in_reset(adev))
mutex_lock(&dm->dc_lock);
/* Need to set POWER_STATE_D0 first or it will not execute
* idle_power_optimizations command to DMUB.
*/
dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
if (!amdgpu_in_reset(adev))
mutex_unlock(&dm->dc_lock);
}
if (amdgpu_in_reset(adev)) {
@ -10964,7 +10974,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
continue;
}
for (j = 0; j < status->plane_count; j++)
dummy_updates[j].surface = status->plane_states[0];
dummy_updates[j].surface = status->plane_states[j];
sort(dummy_updates, status->plane_count,
sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
@ -12299,10 +12309,9 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
/* Overlay cursor not supported on HW before DCN
* DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
* as previous DCN generations, so enable native mode on DCN401 in addition to DCE
* as previous DCN generations, so enable native mode on DCN401
*/
if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 ||
amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
*cursor_mode = DM_CURSOR_NATIVE_MODE;
return 0;
}
@ -12622,6 +12631,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
* need to be added for DC to not disable a plane by mistake
*/
if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) {
if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) {
drm_dbg(dev, "Overlay cursor not supported on DCE\n");
ret = -EINVAL;
goto fail;
}
ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
goto fail;
@ -13139,6 +13154,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
u8 *edid_ext = NULL;
int i;
int j = 0;
int total_ext_block_len;
if (edid == NULL || edid->extensions == 0)
return -ENODEV;
@ -13150,7 +13166,8 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
break;
}
while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
total_ext_block_len = EDID_LENGTH * edid->extensions;
while (j < total_ext_block_len - sizeof(struct amd_vsdb_block)) {
struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);

9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
View File

@ -919,16 +919,15 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
continue;
amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
dc_link = amdgpu_dm_connector->dc_link;
if (!dc_link)
continue;
/*
* Analog connectors may be hot-plugged unlike other connector
* types that don't support HPD. Only poll analog connectors.
*/
use_polling |=
amdgpu_dm_connector->dc_link &&
dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id);
dc_link = amdgpu_dm_connector->dc_link;
use_polling |= dc_connector_supports_analog(dc_link->link_id.id);
/*
* Get a base driver irq reference for hpd ints for the lifetime

2
drivers/gpu/drm/amd/display/dc/Makefile
View File

@ -22,7 +22,7 @@
#
# Makefile for Display Core (dc) component.
DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg
DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg
ifdef CONFIG_DRM_AMD_DC_FP

16
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
View File

@ -766,32 +766,32 @@ static struct wm_table ddr5_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_time_us = 31.0,
.sr_enter_plus_exit_time_us = 33.0,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_time_us = 31.0,
.sr_enter_plus_exit_time_us = 33.0,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_time_us = 31.0,
.sr_enter_plus_exit_time_us = 33.0,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_time_us = 31.0,
.sr_enter_plus_exit_time_us = 33.0,
.valid = true,
},
}

2
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -53,7 +53,7 @@
#include "dpp.h"
#include "timing_generator.h"
#include "abm.h"
#include "virtual/virtual_link_encoder.h"
#include "dio/virtual/virtual_link_encoder.h"
#include "hubp.h"
#include "link_hwss.h"

4
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -37,7 +37,7 @@
#include "dpp.h"
#include "core_types.h"
#include "set_mode_types.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dpcd_defs.h"
#include "link_enc_cfg.h"
#include "link_service.h"
@ -45,7 +45,7 @@
#include "dc_state_priv.h"
#include "dc_stream_priv.h"
#include "virtual/virtual_link_hwss.h"
#include "link/hwss/link_hwss_virtual.h"
#include "link/hwss/link_hwss_dio.h"
#include "link/hwss/link_hwss_dpia.h"
#include "link/hwss/link_hwss_hpo_dp.h"

13
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View File

@ -515,19 +515,6 @@ bool dc_stream_program_cursor_position(
}
}
/* apply manual trigger */
int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
/* trigger event on first pipe with current stream */
if (stream == pipe_ctx->stream) {
pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
break;
}
}
return true;
}

2
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -63,7 +63,7 @@ struct dcn_dsc_reg_state;
struct dcn_optc_reg_state;
struct dcn_dccg_reg_state;
#define DC_VER "3.2.368"
#define DC_VER "3.2.369"
/**
* MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC

54
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
View File

@ -131,54 +131,6 @@ void dccg2_otg_drop_pixel(struct dccg *dccg,
void dccg2_init(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
/* Hardcoded register values for DCN20
* These are specific to 100Mhz refclk
* Different ASICs with different refclk may override this in their own init
*/
REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264);
REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0);
REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);
if (REG(REFCLK_CNTL))
REG_WRITE(REFCLK_CNTL, 0);
}
void dccg2_refclk_setup(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
/* REFCLK programming that must occur after hubbub initialization */
if (REG(REFCLK_CNTL))
REG_WRITE(REFCLK_CNTL, 0);
}
bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464;
}
void dccg2_allow_clock_gating(struct dccg *dccg, bool allow)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
if (allow) {
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
} else {
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF);
}
}
void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1);
}
static const struct dccg_funcs dccg2_funcs = {
@ -187,11 +139,7 @@ static const struct dccg_funcs dccg2_funcs = {
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
.otg_add_pixel = dccg2_otg_add_pixel,
.otg_drop_pixel = dccg2_otg_drop_pixel,
.dccg_init = dccg2_init,
.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
.allow_clock_gating = dccg2_allow_clock_gating,
.enable_memory_low_power = dccg2_enable_memory_low_power,
.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done
.dccg_init = dccg2_init
};
struct dccg *dccg2_create(

18
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
View File

@ -46,9 +46,7 @@
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
SR(DCCG_GATE_DISABLE_CNTL),\
SR(DCCG_GATE_DISABLE_CNTL2)
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
#define DCCG_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@ -83,8 +81,7 @@
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
@ -133,8 +130,7 @@
type DISPCLK_CHG_FWD_CORR_DISABLE;\
type DISPCLK_FREQ_CHANGE_CNTL;\
type OTG_ADD_PIXEL[MAX_PIPES];\
type OTG_DROP_PIXEL[MAX_PIPES];\
type DC_MEM_GLOBAL_PWR_REQ_DIS;
type OTG_DROP_PIXEL[MAX_PIPES];
#define DCCG3_REG_FIELD_LIST(type) \
type HDMICHARCLK0_EN;\
@ -519,14 +515,6 @@ void dccg2_otg_drop_pixel(struct dccg *dccg,
void dccg2_init(struct dccg *dccg);
void dccg2_refclk_setup(struct dccg *dccg);
bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg);
void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);
void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);
struct dccg *dccg2_create(
struct dc_context *ctx,
const struct dccg_registers *regs,

9
drivers/gpu/drm/amd/display/dc/dio/Makefile
View File

@ -23,6 +23,15 @@
#
#
###############################################################################
# VIRTUAL
###############################################################################
DIO_VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o
AMD_DAL_DIO_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/dio/virtual/,$(DIO_VIRTUAL))
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_VIRTUAL)
ifdef CONFIG_DRM_AMD_DC_FP
###############################################################################
# DCN10

2
drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c → drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c
View File

@ -128,5 +128,3 @@ bool virtual_link_encoder_construct(
return true;
}

0
drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h → drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.h
View File

1
drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c → drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c
View File

@ -171,4 +171,3 @@ struct stream_encoder *virtual_stream_encoder_create(
kfree(enc);
return NULL;
}

0
drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h → drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.h
View File

4
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
View File

@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
},
},
.num_states = 5,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_time_us = 31.0,
.sr_enter_plus_exit_time_us = 33.0,
.sr_exit_z8_time_us = 250.0,
.sr_enter_plus_exit_z8_time_us = 350.0,
.fclk_change_latency_us = 24.0,

2
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
View File

@ -655,7 +655,7 @@ __DML_DLL_EXPORT__ void dml_print_soc_bounding_box(const struct soc_bounding_box
dml_print("DML: soc_bbox: refclk_mhz = %f\n", soc->refclk_mhz);
dml_print("DML: soc_bbox: amclk_mhz = %f\n", soc->amclk_mhz);
dml_print("DML: soc_bbox: max_outstanding_reqs = %f\n", soc->max_outstanding_reqs);
dml_print("DML: soc_bbox: max_outstanding_reqs = %d\n", soc->max_outstanding_reqs);
dml_print("DML: soc_bbox: pct_ideal_sdp_bw_after_urgent = %f\n", soc->pct_ideal_sdp_bw_after_urgent);
dml_print("DML: soc_bbox: pct_ideal_fabric_bw_after_urgent = %f\n", soc->pct_ideal_fabric_bw_after_urgent);
dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_only = %f\n", soc->pct_ideal_dram_bw_after_urgent_pixel_only);

21
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
View File

@ -376,10 +376,10 @@ void dpp3_cnv_setup (
tbl_entry.color_space = input_color_space;
if (color_space >= COLOR_SPACE_YCBCR601)
select = INPUT_CSC_SELECT_ICSC;
else
if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
select = INPUT_CSC_SELECT_BYPASS;
else
select = INPUT_CSC_SELECT_ICSC;
dpp3_program_post_csc(dpp_base, color_space, select,
&tbl_entry);
@ -1541,3 +1541,18 @@ bool dpp3_construct(
return true;
}
bool dpp3_should_bypass_post_csc_for_colorspace(enum dc_color_space dc_color_space)
{
switch (dc_color_space) {
case COLOR_SPACE_UNKNOWN:
case COLOR_SPACE_SRGB:
case COLOR_SPACE_XR_RGB:
case COLOR_SPACE_SRGB_LIMITED:
case COLOR_SPACE_MSREF_SCRGB:
case COLOR_SPACE_2020_RGB_FULLRANGE:
case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
return true;
default:
return false;
}
}

4
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
View File

@ -644,4 +644,8 @@ void dpp3_program_cm_dealpha(
void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,
struct dpp_grph_csc_adjustment *adjust);
bool dpp3_should_bypass_post_csc_for_colorspace(
enum dc_color_space dc_color_space);
#endif /* __DC_HWSS_DCN30_H__ */

6
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
View File

@ -206,10 +206,10 @@ void dpp401_dpp_setup(
tbl_entry.color_space = input_color_space;
if (color_space >= COLOR_SPACE_YCBCR601)
select = INPUT_CSC_SELECT_ICSC;
else
if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
select = INPUT_CSC_SELECT_BYPASS;
else
select = INPUT_CSC_SELECT_ICSC;
dpp3_program_post_csc(dpp_base, color_space, select,
&tbl_entry);

31
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
View File

@ -145,21 +145,26 @@ void hubp1_program_tiling(
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
ASSERT(info->gfxversion == DcGfxVersion9);
ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
REG_UPDATE_6(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
NUM_BANKS, log_2(info->gfx9.num_banks),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
NUM_SE, log_2(info->gfx9.num_shader_engines),
NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
if (info->gfxversion == DcGfxVersion9) {
REG_UPDATE_6(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
NUM_BANKS, log_2(info->gfx9.num_banks),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
NUM_SE, log_2(info->gfx9.num_shader_engines),
NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
RB_ALIGNED, info->gfx9.rb_aligned,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
} else {
hubp1_clear_tiling(&hubp1->base);
}
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
RB_ALIGNED, info->gfx9.rb_aligned,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
}
void hubp1_program_size(

24
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
View File

@ -313,18 +313,22 @@ static void hubp2_program_tiling(
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
ASSERT(info->gfxversion == DcGfxVersion9);
ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
REG_UPDATE_3(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
if (info->gfxversion == DcGfxVersion9) {
REG_UPDATE_3(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, 0,
RB_ALIGNED, 0,
PIPE_ALIGNED, 0);
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, 0,
RB_ALIGNED, 0,
PIPE_ALIGNED, 0);
} else {
hubp2_clear_tiling(&hubp2->base);
}
}
void hubp2_program_size(

24
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
View File

@ -321,18 +321,22 @@ void hubp3_program_tiling(
const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
{
ASSERT(info->gfxversion == DcGfxVersion9);
ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
REG_UPDATE_4(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
NUM_PKRS, log_2(info->gfx9.num_pkrs));
if (info->gfxversion == DcGfxVersion9) {
REG_UPDATE_4(DCSURF_ADDR_CONFIG,
NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
NUM_PKRS, log_2(info->gfx9.num_pkrs));
REG_UPDATE_3(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
REG_UPDATE_3(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
} else {
hubp3_clear_tiling(&hubp2->base);
}
}

5
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@ -1887,8 +1887,9 @@ void dcn10_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

29
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@ -357,10 +357,26 @@ void dcn20_enable_power_gating_plane(
void dcn20_dccg_init(struct dce_hwseq *hws)
{
struct dc *dc = hws->ctx->dc;
/*
* set MICROSECOND_TIME_BASE_DIV
* 100Mhz refclk -> 0x120264
* 27Mhz refclk -> 0x12021b
* 48Mhz refclk -> 0x120230
*
*/
REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)
dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);
/*
* set MILLISECOND_TIME_BASE_DIV
* 100Mhz refclk -> 0x1186a0
* 27Mhz refclk -> 0x106978
* 48Mhz refclk -> 0x10bb80
*
*/
REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
/* This value is dependent on the hardware pipeline delay so set once per SOC */
REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
}
void dcn20_disable_vga(
@ -3140,11 +3156,8 @@ void dcn20_fpga_init_hw(struct dc *dc)
dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);
if (hws->funcs.dccg_init)
hws->funcs.dccg_init(hws);
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)
dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);
if (REG(REFCLK_CNTL))
REG_WRITE(REFCLK_CNTL, 0);
//

5
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
View File

@ -367,8 +367,9 @@ void dcn201_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

9
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
View File

@ -33,7 +33,6 @@
#include "vmid.h"
#include "reg_helper.h"
#include "hw/clk_mgr.h"
#include "hw/dccg.h"
#include "dc_dmub_srv.h"
#include "abm.h"
#include "link_service.h"
@ -88,10 +87,12 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_
bool dcn21_s0i3_golden_init_wa(struct dc *dc)
{
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)
return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);
struct dce_hwseq *hws = dc->hwseq;
uint32_t value = 0;
return false;
value = REG_READ(MICROSECOND_TIME_BASE_DIV);
return value != 0x00120464;
}
void dcn21_exit_optimized_pwr_state(

5
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
View File

@ -801,8 +801,9 @@ void dcn30_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

5
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
View File

@ -247,8 +247,9 @@ void dcn31_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

5
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@ -963,8 +963,9 @@ void dcn32_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View File

@ -286,8 +286,7 @@ void dcn35_init_hw(struct dc *dc)
}
if (dc->debug.disable_mem_low_power) {
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power)
dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false);
REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
}
if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

5
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@ -326,8 +326,9 @@ void dcn401_init_hw(struct dc *dc)
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}

4
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
View File

@ -224,9 +224,6 @@ struct dccg_funcs {
void (*otg_drop_pixel)(struct dccg *dccg,
uint32_t otg_inst);
void (*dccg_init)(struct dccg *dccg);
void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
void (*allow_clock_gating)(struct dccg *dccg, bool allow);
void (*enable_memory_low_power)(struct dccg *dccg, bool enable);
void (*set_dpstreamclk_root_clock_gating)(
struct dccg *dccg,
int dp_hpo_inst,
@ -337,7 +334,6 @@ struct dccg_funcs {
void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);
void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);
void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable);
bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg);
};
#endif //__DAL_DCCG_H__

3
drivers/gpu/drm/amd/display/dc/link/Makefile
View File

@ -43,7 +43,8 @@ AMD_DISPLAY_FILES += $(AMD_DAL_LINK_ACCESSORIES)
# hwss
###############################################################################
LINK_HWSS = link_hwss_dio.o link_hwss_dpia.o link_hwss_hpo_dp.o \
link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o
link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o \
link_hwss_virtual.o
AMD_DAL_LINK_HWSS = $(addprefix $(AMDDALPATH)/dc/link/hwss/, \
$(LINK_HWSS))

2
drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c → drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c
View File

@ -23,7 +23,7 @@
*
*/
#include "virtual_link_hwss.h"
#include "link_hwss_virtual.h"
void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx)
{

6
drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h → drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h
View File

@ -22,8 +22,8 @@
* Authors: AMD
*
*/
#ifndef __DC_VIRTUAL_LINK_HWSS_H__
#define __DC_VIRTUAL_LINK_HWSS_H__
#ifndef __DC_LINK_HWSS_VIRTUAL_H__
#define __DC_LINK_HWSS_VIRTUAL_H__
#include "core_types.h"
@ -32,4 +32,4 @@ void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);
void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);
const struct link_hwss *get_virtual_link_hwss(void);
#endif /* __DC_VIRTUAL_LINK_HWSS_H__ */
#endif /* __DC_LINK_HWSS_VIRTUAL_H__ */

8
drivers/gpu/drm/amd/display/dc/link/link_factory.c
View File

@ -564,9 +564,11 @@ static bool construct_phy(struct dc_link *link,
enc_init_data.analog_engine = find_analog_engine(link, &enc_init_data.analog_encoder);
enc_init_data.encoder = link_encoder;
enc_init_data.analog_engine = link_analog_engine;
enc_init_data.hpd_gpio = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
if (link->ctx->dce_version <= DCN_VERSION_4_01)
enc_init_data.hpd_gpio = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
else
enc_init_data.hpd_gpio = NULL;
if (enc_init_data.hpd_gpio) {
dal_gpio_open(enc_init_data.hpd_gpio, GPIO_MODE_INTERRUPT);
dal_gpio_unlock_pin(enc_init_data.hpd_gpio);

14
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
View File

@ -34,6 +34,7 @@
link->ctx->logger
#define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B
#define DP_SINK_ENABLE_FRAME_SKIPPING_MODE_SHIFT (5)
static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz)
{
@ -89,6 +90,7 @@ static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_s
union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 };
union dpcd_alpm_configuration alpm_config;
uint8_t data = 0;
replay_context.controllerId = CONTROLLER_ID_UNDEFINED;
@ -186,6 +188,14 @@ static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_s
DP_RECEIVER_ALPM_CONFIG,
&alpm_config.raw,
sizeof(alpm_config.raw));
//Enable frame skipping
if (link->replay_settings.config.frame_skip_supported)
data = data | (1 << DP_SINK_ENABLE_FRAME_SKIPPING_MODE_SHIFT);
dm_helpers_dp_write_dpcd(link->ctx, link,
DP_SINK_PR_ENABLE_AND_CONFIGURATION,
(uint8_t *)&(data), sizeof(uint8_t));
}
return true;
@ -323,10 +333,10 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
pipe_ctx->stream->timing.dsc_cfg.num_slices_v;
if (dc_is_embedded_signal(link->connector_signal))
cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C;
cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1C;
else
// For external DP, use option 1-A
cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A;
cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1A;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;

9
drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c
View File

@ -136,8 +136,13 @@ enum hpd_source_id get_hpd_line(struct dc_link *link)
hpd_id = HPD_SOURCEID_UNKNOWN;
hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
/* Use GPIO path where supported, otherwise use hardware encoder path */
if (link->ctx && link->ctx->dce_version <= DCN_VERSION_4_01) {
hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
} else {
hpd = NULL;
}
if (hpd) {
switch (dal_irq_get_source(hpd)) {

2
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
View File

@ -31,7 +31,7 @@
#include "resource.h"
#include "clk_mgr.h"
#include "include/irq_service_interface.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dce110/dce110_timing_generator.h"
#include "irq/dce110/irq_service_dce110.h"

2
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
View File

@ -35,7 +35,7 @@
#include "dce112/dce112_resource.h"
#include "dce110/dce110_resource.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce120/dce120_timing_generator.h"
#include "irq/dce120/irq_service_dce120.h"
#include "dce/dce_opp.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
View File

@ -48,7 +48,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h"
#include "dcn10/dcn10_hubp.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
View File

@ -55,7 +55,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dcn20/dcn20_dccg.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
View File

@ -51,7 +51,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dce/dce_aux.h"
#include "dce/dce_i2c.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
View File

@ -57,7 +57,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dml/display_mode_vba.h"
#include "dcn20/dcn20_dccg.h"
#include "dcn21/dcn21_dccg.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
View File

@ -55,7 +55,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dcn30/dcn30_dccg.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
View File

@ -54,7 +54,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dcn301/dcn301_dccg.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
View File

@ -64,7 +64,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dml/dcn31/dcn31_fpu.h"

2
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
View File

@ -66,7 +66,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dml/dcn31/dcn31_fpu.h"

10
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
View File

@ -63,7 +63,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dml/dcn31/dcn31_fpu.h"
@ -1230,12 +1230,12 @@ static struct stream_encoder *dcn315_stream_encoder_create(
/*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/
/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
if (eng_id <= ENGINE_ID_DIGF) {
vpg_inst = eng_id;
afmt_inst = eng_id;
} else
if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
return NULL;
vpg_inst = eng_id;
afmt_inst = eng_id;
enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
vpg = dcn31_vpg_create(ctx, vpg_inst);
afmt = dcn31_afmt_create(ctx, afmt_inst);

10
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
View File

@ -63,7 +63,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dml/dcn31/dcn31_fpu.h"
@ -1223,12 +1223,12 @@ static struct stream_encoder *dcn316_stream_encoder_create(
int afmt_inst;
/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
if (eng_id <= ENGINE_ID_DIGF) {
vpg_inst = eng_id;
afmt_inst = eng_id;
} else
if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
return NULL;
vpg_inst = eng_id;
afmt_inst = eng_id;
enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
vpg = dcn31_vpg_create(ctx, vpg_inst);
afmt = dcn31_afmt_create(ctx, afmt_inst);

10
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
View File

@ -65,7 +65,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dml/display_mode_vba.h"
#include "dcn32/dcn32_dccg.h"
#include "dcn10/dcn10_resource.h"
@ -1211,12 +1211,12 @@ static struct stream_encoder *dcn32_stream_encoder_create(
int afmt_inst;
/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
if (eng_id <= ENGINE_ID_DIGF) {
vpg_inst = eng_id;
afmt_inst = eng_id;
} else
if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
return NULL;
vpg_inst = eng_id;
afmt_inst = eng_id;
enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
vpg = dcn32_vpg_create(ctx, vpg_inst);
afmt = dcn32_afmt_create(ctx, afmt_inst);

10
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
View File

@ -68,7 +68,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dml/display_mode_vba.h"
#include "dcn32/dcn32_dccg.h"
#include "dcn10/dcn10_resource.h"
@ -1192,12 +1192,12 @@ static struct stream_encoder *dcn321_stream_encoder_create(
int afmt_inst;
/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
if (eng_id <= ENGINE_ID_DIGF) {
vpg_inst = eng_id;
afmt_inst = eng_id;
} else
if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
return NULL;
vpg_inst = eng_id;
afmt_inst = eng_id;
enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
vpg = dcn321_vpg_create(ctx, vpg_inst);
afmt = dcn321_afmt_create(ctx, afmt_inst);

10
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View File

@ -70,7 +70,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dcn35/dcn35_dccg.h"
@ -1274,12 +1274,12 @@ static struct stream_encoder *dcn35_stream_encoder_create(
int afmt_inst;
/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
if (eng_id <= ENGINE_ID_DIGF) {
vpg_inst = eng_id;
afmt_inst = eng_id;
} else
if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
return NULL;
vpg_inst = eng_id;
afmt_inst = eng_id;
enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
vpg = dcn31_vpg_create(ctx, vpg_inst);
afmt = dcn31_afmt_create(ctx, afmt_inst);

10
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
View File

@ -49,7 +49,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dcn35/dcn35_dccg.h"
@ -1254,12 +1254,12 @@ static struct stream_encoder *dcn35_stream_encoder_create(
int afmt_inst;
/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
if (eng_id <= ENGINE_ID_DIGF) {
vpg_inst = eng_id;
afmt_inst = eng_id;
} else
if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
return NULL;
vpg_inst = eng_id;
afmt_inst = eng_id;
enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
vpg = dcn31_vpg_create(ctx, vpg_inst);
afmt = dcn31_afmt_create(ctx, afmt_inst);

4
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
View File

@ -49,7 +49,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
#include "dml/display_mode_vba.h"
#include "dcn35/dcn35_dccg.h"
@ -775,7 +775,7 @@ static const struct dc_debug_options debug_defaults_drv = {
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
.enable_legacy_fast_update = false,
};
static const struct dc_panel_config panel_config_defaults = {

2
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@ -47,7 +47,7 @@
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "clk_mgr.h"
#include "virtual/virtual_stream_encoder.h"
#include "dio/virtual/virtual_stream_encoder.h"
#include "dml/display_mode_vba.h"
#include "dcn401/dcn401_dccg.h"
#include "dcn10/dcn10_resource.h"

30
drivers/gpu/drm/amd/display/dc/virtual/Makefile
View File

@ -1,30 +0,0 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
#
# Makefile for the virtual sub-component of DAL.
# It provides the control and status of HW CRTC block.
VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o virtual_link_hwss.o
AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL))
AMD_DISPLAY_FILES += $(AMD_DAL_VIRTUAL)

15
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@ -1638,6 +1638,11 @@ enum dmub_gpint_command {
* DESC: Initiates IPS wake sequence.
*/
DMUB_GPINT__IPS_DEBUG_WAKE = 137,
/**
* DESC: Do panel power off sequence
* ARGS: 1 - Power off
*/
DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138,
};
/**
@ -4408,6 +4413,7 @@ enum dmub_cmd_panel_replay_type {
enum dmub_cmd_panel_replay_state_update_subtype {
PR_STATE_UPDATE_COASTING_VTOTAL = 0x1,
PR_STATE_UPDATE_SYNC_MODE = 0x2,
PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3,
};
enum dmub_cmd_panel_replay_general_subtype {
@ -6701,6 +6707,13 @@ struct dmub_rb_cmd_pr_copy_settings {
struct dmub_cmd_pr_copy_settings_data data;
};
union dmub_pr_runtime_flags {
struct {
uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR
} bitfields;
uint32_t u32All;
};
struct dmub_cmd_pr_update_state_data {
/**
* Panel Instance.
@ -6719,6 +6732,8 @@ struct dmub_cmd_pr_update_state_data {
*/
uint32_t coasting_vtotal;
uint32_t sync_mode;
union dmub_pr_runtime_flags pr_runtime_flags;
};
struct dmub_cmd_pr_general_cmd_data {

5
drivers/gpu/drm/amd/include/kgd_pp_interface.h
View File

@ -1829,4 +1829,9 @@ struct amdgpu_partition_metrics_v1_1 {
struct gpu_metrics_attr metrics_attrs[];
};
enum amdgpu_xgmi_link_status {
AMDGPU_XGMI_LINK_INACTIVE = 0,
AMDGPU_XGMI_LINK_ACTIVE = 1,
};
#endif

29
drivers/gpu/drm/amd/pm/amdgpu_pm.c
View File

@ -243,11 +243,11 @@ static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
enum amd_pm_state_type state;
int ret;
if (strncmp("battery", buf, strlen("battery")) == 0)
if (sysfs_streq(buf, "battery"))
state = POWER_STATE_TYPE_BATTERY;
else if (strncmp("balanced", buf, strlen("balanced")) == 0)
else if (sysfs_streq(buf, "balanced"))
state = POWER_STATE_TYPE_BALANCED;
else if (strncmp("performance", buf, strlen("performance")) == 0)
else if (sysfs_streq(buf, "performance"))
state = POWER_STATE_TYPE_PERFORMANCE;
else
return -EINVAL;
@ -363,29 +363,28 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
enum amd_dpm_forced_level level;
int ret = 0;
if (strncmp("low", buf, strlen("low")) == 0) {
if (sysfs_streq(buf, "low"))
level = AMD_DPM_FORCED_LEVEL_LOW;
} else if (strncmp("high", buf, strlen("high")) == 0) {
else if (sysfs_streq(buf, "high"))
level = AMD_DPM_FORCED_LEVEL_HIGH;
} else if (strncmp("auto", buf, strlen("auto")) == 0) {
else if (sysfs_streq(buf, "auto"))
level = AMD_DPM_FORCED_LEVEL_AUTO;
} else if (strncmp("manual", buf, strlen("manual")) == 0) {
else if (sysfs_streq(buf, "manual"))
level = AMD_DPM_FORCED_LEVEL_MANUAL;
} else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
else if (sysfs_streq(buf, "profile_exit"))
level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
} else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
else if (sysfs_streq(buf, "profile_standard"))
level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
} else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
else if (sysfs_streq(buf, "profile_min_sclk"))
level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
} else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
else if (sysfs_streq(buf, "profile_min_mclk"))
level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
} else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
else if (sysfs_streq(buf, "profile_peak"))
level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
} else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
else if (sysfs_streq(buf, "perf_determinism"))
level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
} else {
else
return -EINVAL;
}
ret = amdgpu_pm_get_access(adev);
if (ret < 0)

5
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
View File

@ -3464,6 +3464,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
max_sclk = 60000;
max_mclk = 80000;
}
if ((adev->pdev->device == 0x666f) &&
(adev->pdev->revision == 0x00)) {
max_sclk = 80000;
max_mclk = 95000;
}
} else if (adev->asic_type == CHIP_OLAND) {
if ((adev->pdev->revision == 0xC7) ||
(adev->pdev->revision == 0x80) ||

7
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -810,7 +810,7 @@ static int smu_early_init(struct amdgpu_ip_block *ip_block)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.state = SMU_BACO_STATE_EXIT;
smu->smu_baco.platform_support = false;
smu->smu_baco.maco_support = false;
smu->user_dpm_profile.fan_mode = -1;
@ -2120,9 +2120,8 @@ static int smu_reset_mp1_state(struct smu_context *smu)
int ret = 0;
if ((!adev->in_runpm) && (!adev->in_suspend) &&
(!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) ==
IP_VERSION(13, 0, 10) &&
!amdgpu_device_has_display_hardware(adev))
(!amdgpu_in_reset(adev)) && !smu->is_apu &&
amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0))
ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
return ret;

1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View File

@ -536,7 +536,6 @@ enum smu_reset_mode {
enum smu_baco_state {
SMU_BACO_STATE_ENTER = 0,
SMU_BACO_STATE_EXIT,
SMU_BACO_STATE_NONE,
};
struct smu_baco_context {

2
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
View File

@ -226,8 +226,6 @@ int smu_v15_0_deep_sleep_control(struct smu_context *smu,
int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu);
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu);
int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu,
void **table,
uint32_t *size,

23
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View File

@ -2615,21 +2615,11 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
u32 smu_version;
int ret;
/* SRIOV does not support SMU mode1 reset */
if (amdgpu_sriov_vf(adev))
return false;
/* PMFW support is available since 78.41 */
ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
if (ret)
return false;
if (smu_version < 0x004e2900)
return false;
return true;
}
@ -2778,13 +2768,7 @@ static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
switch (mp1_state) {
case PP_MP1_STATE_UNLOAD:
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_PrepareMp1ForUnload,
0x55, NULL);
if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT)
ret = smu_v13_0_disable_pmfw_state(smu);
ret = smu_cmn_set_mp1_state(smu, mp1_state);
break;
default:
/* Ignore others */
@ -2828,8 +2812,9 @@ static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
/* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */
smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, &param);
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_Mode1Reset, param, NULL);
ret = smu_cmn_send_debug_smc_msg_with_param(smu,
DEBUGSMC_MSG_Mode1Reset, param);
break;
case IP_VERSION(13, 0, 10):

3
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
View File

@ -823,6 +823,9 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp
idx++;
}
xcp_metrics->accumulation_counter = metrics->AccumulationCounter;
xcp_metrics->firmware_timestamp = metrics->Timestamp;
return sizeof(*xcp_metrics);
}

2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
View File

@ -2668,6 +2668,8 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
idx++;
}
}
xcp_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
xcp_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
return sizeof(*xcp_metrics);
}

8
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
View File

@ -140,7 +140,7 @@ extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv;
SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \
SMU_MTYPE(U64), system_clock_counter); \
SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \
SMU_MTYPE(U32), accumulation_counter); \
SMU_MTYPE(U64), accumulation_counter); \
SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \
SMU_MTYPE(U32), prochot_residency_acc); \
SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \
@ -259,7 +259,11 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table,
SMU_13_0_6_MAX_XCC); \
SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \
SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \
SMU_13_0_6_MAX_XCC);
SMU_13_0_6_MAX_XCC); \
SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \
SMU_MTYPE(U64), accumulation_counter); \
SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \
SMU_MTYPE(U64), firmware_timestamp);
DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_partition_metrics,
SMU_13_0_6_PARTITION_METRICS_FIELDS);

45
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
View File

@ -74,6 +74,17 @@ static const struct smu_feature_bits smu_v13_0_7_dpm_features = {
#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
#define mmMP1_SMN_C2PMSG_75 0x028b
#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_53 0x0275
#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_54 0x0276
#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
#define DEBUGSMC_MSG_Mode1Reset 2
#define PP_OD_FEATURE_GFXCLK_FMIN 0
#define PP_OD_FEATURE_GFXCLK_FMAX 1
#define PP_OD_FEATURE_UCLK_FMIN 2
@ -2734,6 +2745,36 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
return ret;
}
static int smu_v13_0_7_mode1_reset(struct smu_context *smu)
{
int ret;
ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
if (!ret) {
/* disable mmio access while doing mode 1 reset*/
smu->adev->no_hw_access = true;
/* ensure no_hw_access is globally visible before any MMIO */
smp_mb();
msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
}
return ret;
}
static void smu_v13_0_7_init_msg_ctl(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map);
/* Set up debug mailbox registers */
ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;
}
static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.init_allowed_features = smu_v13_0_7_init_allowed_features,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@ -2795,7 +2836,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.baco_enter = smu_v13_0_baco_enter,
.baco_exit = smu_v13_0_baco_exit,
.mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
.mode1_reset = smu_v13_0_mode1_reset,
.mode1_reset = smu_v13_0_7_mode1_reset,
.set_mp1_state = smu_v13_0_7_set_mp1_state,
.set_df_cstate = smu_v13_0_7_set_df_cstate,
.gpo_control = smu_v13_0_gpo_control,
@ -2814,5 +2855,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
smu->workload_map = smu_v13_0_7_workload_map;
smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION;
smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map);
smu_v13_0_7_init_msg_ctl(smu);
}

8
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
View File

@ -1726,14 +1726,6 @@ int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu)
return ret;
}
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
int smu_v15_0_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long input[], uint32_t size)

165
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
View File

@ -52,18 +52,11 @@
#define mmMP1_SMN_C2PMSG_32 0x0060
#define mmMP1_SMN_C2PMSG_32_BASE_IDX 1
/* MALLPowerController message arguments (Defines for the Cache mode control) */
#define SMU_MALL_PMFW_CONTROL 0
#define SMU_MALL_DRIVER_CONTROL 1
#define mmMP1_SMN_C2PMSG_33 0x0061
#define mmMP1_SMN_C2PMSG_33_BASE_IDX 1
/*
* MALLPowerState message arguments
* (Defines for the Allocate/Release Cache mode if in driver mode)
*/
#define SMU_MALL_EXIT_PG 0
#define SMU_MALL_ENTER_PG 1
#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
#define mmMP1_SMN_C2PMSG_34 0x0062
#define mmMP1_SMN_C2PMSG_34_BASE_IDX 1
#define SMU_15_0_UMD_PSTATE_GFXCLK 700
#define SMU_15_0_UMD_PSTATE_SOCCLK 678
@ -240,6 +233,102 @@ static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en)
return ret;
}
static int smu_v15_0_0_update_table(struct smu_context *smu,
enum smu_table_id table_index,
int argument,
void *table_data,
bool drv2smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct amdgpu_device *adev = smu->adev;
struct smu_table *table = &smu_table->driver_table;
int table_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_TABLE,
table_index);
uint64_t address;
uint32_t table_size;
int ret;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
return -EINVAL;
table_size = smu_table->tables[table_index].size;
if (drv2smu) {
memcpy(table->cpu_addr, table_data, table_size);
/*
* Flush hdp cache: to guard the content seen by
* GPU is consitent with CPU.
*/
amdgpu_hdp_flush(adev, NULL);
}
address = table->mc_address;
struct smu_msg_args args = {
.msg = drv2smu ?
SMU_MSG_TransferTableDram2Smu :
SMU_MSG_TransferTableSmu2Dram,
.num_args = 3,
.num_out_args = 0,
};
args.args[0] = table_id;
args.args[1] = (uint32_t)lower_32_bits(address);
args.args[2] = (uint32_t)upper_32_bits(address);
ret = ctl->ops->send_msg(ctl, &args);
if (ret)
return ret;
if (!drv2smu) {
amdgpu_hdp_invalidate(adev, NULL);
memcpy(table_data, table->cpu_addr, table_size);
}
return 0;
}
static int smu_v15_0_0_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
static int smu_v15_0_0_get_metrics_table(struct smu_context *smu,
void *metrics_table,
bool bypass_cache)
{
struct smu_table_context *smu_table = &smu->smu_table;
uint32_t table_size =
smu_table->tables[SMU_TABLE_SMU_METRICS].size;
int ret;
if (bypass_cache ||
!smu_table->metrics_time ||
time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
ret = smu_v15_0_0_update_table(smu,
SMU_TABLE_SMU_METRICS,
0,
smu_table->metrics_table,
false);
if (ret) {
dev_info(smu->adev->dev, "Failed to export SMU15_0_0 metrics table!\n");
return ret;
}
smu_table->metrics_time = jiffies;
}
if (metrics_table)
memcpy(metrics_table, smu_table->metrics_table, table_size);
return 0;
}
static int smu_v15_0_0_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
@ -249,7 +338,7 @@ static int smu_v15_0_0_get_smu_metrics_data(struct smu_context *smu,
SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
int ret = 0;
ret = smu_cmn_get_metrics_table(smu, NULL, false);
ret = smu_v15_0_0_get_metrics_table(smu, NULL, false);
if (ret)
return ret;
@ -443,12 +532,36 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu,
return ret;
}
static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu,
struct smu_feature_bits *feature_mask)
{
int ret;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
if (!feature_mask)
return -EINVAL;
struct smu_msg_args args = {
.msg = SMU_MSG_GetEnabledSmuFeatures,
.num_args = 0,
.num_out_args = 2,
};
ret = ctl->ops->send_msg(ctl, &args);
if (!ret)
smu_feature_bits_from_arr32(feature_mask, args.out_args,
SMU_FEATURE_NUM_DEFAULT);
return ret;
}
static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
ret = smu_v15_0_0_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
@ -524,7 +637,7 @@ static ssize_t smu_v15_0_0_get_gpu_metrics(struct smu_context *smu,
SmuMetrics_t metrics;
int ret = 0;
ret = smu_cmn_get_metrics_table(smu, &metrics, true);
ret = smu_v15_0_0_get_metrics_table(smu, &metrics, false);
if (ret)
return ret;
@ -979,26 +1092,21 @@ static int smu_v15_0_0_set_soft_freq_limited_range(struct smu_context *smu,
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
msg_set_min = SMU_MSG_SetHardMinGfxClk;
msg_set_min = SMU_MSG_SetSoftMinGfxclk;
msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
break;
case SMU_FCLK:
msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
msg_set_min = SMU_MSG_SetSoftMinFclk;
msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
break;
case SMU_SOCCLK:
msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
msg_set_min = SMU_MSG_SetSoftMinSocclkByFreq;
msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
break;
case SMU_VCLK:
case SMU_DCLK:
msg_set_min = SMU_MSG_SetHardMinVcn0;
msg_set_max = SMU_MSG_SetSoftMaxVcn0;
break;
case SMU_VCLK1:
case SMU_DCLK1:
msg_set_min = SMU_MSG_SetHardMinVcn1;
msg_set_max = SMU_MSG_SetSoftMaxVcn1;
msg_set_min = SMU_MSG_SetSoftMinVcn;
msg_set_max = SMU_MSG_SetSoftMaxVcn;
break;
default:
return -EINVAL;
@ -1315,14 +1423,13 @@ static const struct pptable_funcs smu_v15_0_0_ppt_funcs = {
.system_features_control = smu_v15_0_0_system_features_control,
.dpm_set_vcn_enable = smu_v15_0_set_vcn_enable,
.dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable,
.set_default_dpm_table = smu_v15_0_set_default_dpm_tables,
.set_default_dpm_table = smu_v15_0_0_set_default_dpm_tables,
.read_sensor = smu_v15_0_0_read_sensor,
.is_dpm_running = smu_v15_0_0_is_dpm_running,
.set_watermarks_table = smu_v15_0_0_set_watermarks_table,
.get_gpu_metrics = smu_v15_0_0_get_gpu_metrics,
.get_enabled_mask = smu_cmn_get_enabled_mask,
.get_enabled_mask = smu_v15_0_0_get_enabled_mask,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v15_0_set_driver_table_location,
.gfx_off_control = smu_v15_0_gfx_off_control,
.mode2_reset = smu_v15_0_0_mode2_reset,
.get_dpm_ultimate_freq = smu_v15_0_common_get_dpm_ultimate_freq,
@ -1347,7 +1454,9 @@ static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu)
ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30);
ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31);
ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32);
ctl->config.num_arg_regs = 1;
ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_33);
ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_34);
ctl->config.num_arg_regs = 3;
ctl->ops = &smu_msg_v1_ops;
ctl->default_timeout = adev->usec_timeout * 20;
ctl->message_map = smu_v15_0_0_message_map;

5
drivers/gpu/drm/radeon/si_dpm.c
View File

@ -2925,6 +2925,11 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
max_sclk = 60000;
max_mclk = 80000;
}
if ((rdev->pdev->device == 0x666f) &&
(rdev->pdev->revision == 0x00)) {
max_sclk = 80000;
max_mclk = 95000;
}
} else if (rdev->family == CHIP_OLAND) {
if ((rdev->pdev->revision == 0xC7) ||
(rdev->pdev->revision == 0x80) ||

1
include/uapi/drm/amdgpu_drm.h
View File

@ -1667,6 +1667,7 @@ struct drm_amdgpu_info_uq_metadata {
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
#define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */
#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
#if defined(__cplusplus)