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drm/vc4: Add additional warn_on for incorrect revisions

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Some code path in vc4 are conditional to a generation and cannot be
executed on others. Let's put a WARN_ON if that ever happens.

Signed-off-by: Maxime Ripard <mripard@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025-drm-vc4-2712-support-v2-26-35efa83c8fc0@raspberrypi.com
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
This commit is contained in:
Maxime Ripard 2024-10-25 18:15:57 +01:00 committed by Dave Stevenson
parent 88c065c739
commit 3e048861c5
3 changed files with 51 additions and 2 deletions
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30
drivers/gpu/drm/vc4/vc4_hvs.c
View File

@ -419,12 +419,15 @@ static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
struct vc4_crtc *vc4_crtc)
{
struct drm_device *drm = &hvs->vc4->base;
struct vc4_dev *vc4 = hvs->vc4;
struct drm_device *drm = &vc4->base;
struct drm_crtc *crtc = &vc4_crtc->base;
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
int idx;
u32 i;
WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
if (!drm_dev_enter(drm, &idx))
return;
@ -474,6 +477,8 @@ u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
u8 field = 0;
int idx;
WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);
if (!drm_dev_enter(drm, &idx))
return 0;
@ -530,6 +535,8 @@ int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
u32 reg;
int ret;
WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);
switch (vc4->gen) {
case VC4_GEN_4:
return output;
@ -621,6 +628,8 @@ static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
u32 dispctrl;
int idx;
WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
if (!drm_dev_enter(drm, &idx))
return -ENODEV;
@ -682,6 +691,8 @@ static int vc6_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
u32 disp_ctrl1;
int idx;
WARN_ON_ONCE(vc4->gen < VC4_GEN_6_C);
if (!drm_dev_enter(drm, &idx))
return -ENODEV;
@ -707,9 +718,12 @@ static int vc6_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
static void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
{
struct drm_device *drm = &hvs->vc4->base;
struct vc4_dev *vc4 = hvs->vc4;
struct drm_device *drm = &vc4->base;
int idx;
WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
if (!drm_dev_enter(drm, &idx))
return;
@ -740,6 +754,8 @@ static void __vc6_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
struct drm_device *drm = &vc4->base;
int idx;
WARN_ON_ONCE(vc4->gen < VC4_GEN_6_C);
if (!drm_dev_enter(drm, &idx))
return;
@ -927,6 +943,8 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
bool found = false;
int idx;
WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);
if (!drm_dev_enter(dev, &idx)) {
vc4_crtc_send_vblank(crtc);
return;
@ -1011,6 +1029,8 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
if (crtc->state->color_mgmt_changed) {
u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
if (crtc->state->gamma_lut) {
vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
dispbkgndx |= SCALER_DISPBKGND_GAMMA;
@ -1040,6 +1060,8 @@ void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
u32 dispctrl;
int idx;
WARN_ON(vc4->gen > VC4_GEN_5);
if (!drm_dev_enter(drm, &idx))
return;
@ -1060,6 +1082,8 @@ void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
u32 dispctrl;
int idx;
WARN_ON(vc4->gen > VC4_GEN_5);
if (!drm_dev_enter(drm, &idx))
return;
@ -1094,6 +1118,8 @@ static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
u32 status;
u32 dspeislur;
WARN_ON(vc4->gen > VC4_GEN_5);
/*
* NOTE: We don't need to protect the register access using
* drm_dev_enter() there because the interrupt handler lifetime

6
drivers/gpu/drm/vc4/vc4_kms.c
View File

@ -138,6 +138,8 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
struct drm_color_ctm *ctm = ctm_state->ctm;
WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
if (ctm_state->fifo) {
HVS_WRITE(SCALER_OLEDCOEF2,
VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
@ -213,6 +215,8 @@ static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
struct drm_crtc *crtc;
unsigned int i;
WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
@ -256,6 +260,8 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
unsigned int i;
u32 reg;
WARN_ON_ONCE(vc4->gen != VC4_GEN_5);
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

17
drivers/gpu/drm/vc4/vc4_plane.c
View File

@ -566,8 +566,11 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
{
struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
u32 scale, recip;
WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);
scale = src / dst;
/* The specs note that while the reciprocal would be defined
@ -593,10 +596,13 @@ static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst,
u32 xy, int channel)
{
struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
u32 scale = src / dst;
s32 offset, offset2;
s32 phase;
WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);
/*
* Start the phase at 1/2 pixel from the 1st pixel at src_x.
* 1/4 pixel for YUV.
@ -825,8 +831,11 @@ static size_t vc6_upm_size(const struct drm_plane_state *state,
static void vc4_write_scaling_parameters(struct drm_plane_state *state,
int channel)
{
struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);
/* Ch0 H-PPF Word 0: Scaling Parameters */
if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
vc4_write_ppf(vc4_state, vc4_state->src_w[channel],
@ -1113,6 +1122,11 @@ static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
{
struct drm_device *dev = state->state->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
if (!state->fb->format->has_alpha)
return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
SCALER_POS2_ALPHA_MODE);
@ -1137,6 +1151,9 @@ static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
struct drm_device *dev = state->state->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
WARN_ON_ONCE(vc4->gen != VC4_GEN_5 && vc4->gen != VC4_GEN_6_C &&
vc4->gen != VC4_GEN_6_D);
switch (vc4->gen) {
default:
case VC4_GEN_5: