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drm/amd/display: Enable mem low power control for DCN3.1 sub-IP blocks

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[WHY]
Sequences to handle powering down these sub-IP blocks are now ready for use

Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michael Strauss 2021-09-01 13:49:37 -04:00 committed by Alex Deucher
parent 0c55b63ba3
commit 3da35006fe
1 changed files with 8 additions and 8 deletions
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16
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
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@ -1009,15 +1009,15 @@ static const struct dc_debug_options debug_defaults_drv = {
.use_max_lb = true,
.enable_mem_low_power = {
.bits = {
.vga = false,
.i2c = false,
.vga = true,
.i2c = true,
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
.dscl = false,
.cm = false,
.mpc = false,
.optc = false,
.vpg = false,
.afmt = false,
.dscl = true,
.cm = true,
.mpc = true,
.optc = true,
.vpg = true,
.afmt = true,
}
},
.optimize_edp_link_rate = true,