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i.MX fixes for 7.0:

Browse Source 
- Revert the NAND property move that broke compatibility across multiple
   imx6/imx7 device trees
 - Fix imx8mq-librem5 power management by bumping BUCK1 suspend voltage to
   0.85V and reverting problematic DVS voltage changes
 - Correct eMMC pad configuration for imx93-tqma9352 and imx91-tqma9131
 - Change usdhc tuning step for eMMC and SD on imx93-9x9-qsb
 - Correct gpu_ahb clock frequency for imx8mq
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Merge tag 'imx-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into arm/fixes

i.MX fixes for 7.0:

- Revert the NAND property move that broke compatibility across multiple
  imx6/imx7 device trees
- Fix imx8mq-librem5 power management by bumping BUCK1 suspend voltage to
  0.85V and reverting problematic DVS voltage changes
- Correct eMMC pad configuration for imx93-tqma9352 and imx91-tqma9131
- Change usdhc tuning step for eMMC and SD on imx93-9x9-qsb
- Correct gpu_ahb clock frequency for imx8mq

* tag 'imx-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux:
  arm64: dts: imx8mq-librem5: Bump BUCK1 suspend voltage up to 0.85V
  Revert "arm64: dts: imx8mq-librem5: Set the DVS voltages lower"
  Revert "ARM: dts: imx: move nand related property under nand@0"
  arm64: dts: imx93-tqma9352: improve eMMC pad configuration
  arm64: dts: imx91-tqma9131: improve eMMC pad configuration
  arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD
  arm64: dts: imx8mq: Set the correct gpu_ahb clock frequency

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-03-27 12:50:36 +01:00
commit 3d53a7a286
21 changed files with 56 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
View File

@ -36,12 +36,8 @@ &clks {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
View File

@ -172,12 +172,8 @@ eth_phy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
View File

@ -102,12 +102,8 @@ ethphy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
View File

@ -73,12 +73,8 @@ ethphy: ethernet-phy@3 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@ -260,14 +260,10 @@ fixed-link {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c3 {

6
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
View File

@ -252,13 +252,9 @@ etnphy: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@ -133,12 +133,8 @@ ethphy1: ethernet-phy@1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
View File

@ -101,12 +101,8 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
View File

@ -63,12 +63,8 @@ ethphy1: ethernet-phy@1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c1 {

6
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
View File

@ -296,13 +296,9 @@ &fec2 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&i2c2 {

12
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
View File

@ -160,15 +160,11 @@ &gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */

12
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
View File

@ -43,15 +43,11 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <0>;
nand-ecc-step-size = <0>;
nand-on-flash-bbt;
};
};
&iomuxc {

6
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
View File

@ -60,12 +60,8 @@ ethphy0: ethernet-phy@0 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&uart1 {

6
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
View File

@ -25,12 +25,8 @@ usdhc2_pwrseq: usdhc2-pwrseq {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
};
};
&snvs_poweroff {

8
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
View File

@ -375,14 +375,10 @@ &gpio7 {
/* NAND on such SKUs */
&gpmi {
fsl,use-minimum-ecc;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand@0 {
reg = <0>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
};
};
/* On-module Power I2C */

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
View File

@ -7,7 +7,7 @@
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <950000>;
opp-microvolt = <1000000>;
};
};

24
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -880,9 +880,9 @@ buck1_reg: BUCK1 {
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <880000>;
rohm,dvs-idle-voltage = <820000>;
rohm,dvs-suspend-voltage = <810000>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <850000>;
regulator-always-on;
};
@ -892,8 +892,8 @@ buck2_reg: BUCK2 {
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <950000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
regulator-always-on;
};
@ -902,14 +902,14 @@ buck3_reg: BUCK3 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <850000>;
rohm,dvs-run-voltage = <900000>;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
rohm,dvs-run-voltage = <930000>;
rohm,dvs-run-voltage = <1000000>;
};
buck5_reg: BUCK5 {
@ -1448,13 +1448,3 @@ &wdog1 {
fsl,ext-reset-output;
status = "okay";
};
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <850000>;
};
opp-1500000000 {
opp-microvolt = <950000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1632,7 +1632,7 @@ gpu: gpu@38000000 {
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL>;
assigned-clock-rates = <800000000>, <800000000>,
<800000000>, <800000000>, <0>;
<800000000>, <400000000>, <0>;
power-domains = <&pgc_gpu>;
};

20
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
View File

@ -272,20 +272,20 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = /* PD | FSEL 3 | DSE X5 */
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x59e>,
/* HYS | FSEL 0 | no drive */
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
/* HYS | FSEL 3 | X5 */
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x4000139e>,
/* HYS | FSEL 3 | X4 */
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e>;
};
pinctrl_wdog: wdoggrp {

2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@ -507,6 +507,7 @@ &usdhc1 {
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
fsl,tuning-step = <1>;
status = "okay";
};
@ -519,6 +520,7 @@ &usdhc2 {
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-mmc;
fsl,tuning-step = <1>;
status = "okay";
};

26
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@ -271,21 +271,21 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x106
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
/* PD | FSEL 3 | DSE X5 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
/* PD | FSEL 3 | DSE X4 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e
/* HYS | FSEL 0 | no drive */
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
/* HYS | FSEL 3 | X5 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
/* HYS | FSEL 3 | X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
/* HYS | PU | FSEL 3 | DSE X4 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
/* HYS | PU | FSEL 3 | DSE X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
>;
};