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arm64: tegra: Changes for v6.20-rc1
This update improves Device Tree support for 64-bit Tegra platforms, specifically focusing on the Smaug board and the Tegra264 SoC. It enables full USB-C functionality on Smaug by adding role-switching support and enabling DisplayPort altmode. For Tegra264, it introduces nodes for Command Queue Virtualization (CMDQV) in the SMMU, adds the Data Backbone (DBB) clock for the memory controller, and corrects CPU compatible strings to match the Neoverse V3AE core. Additionally, it performs a cleanup by removing redundant status = "okay" properties across Tegra186, Tegra194, Tegra234, and Tegra264 files. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmlskkoACgkQ3SOs138+ s6Hs7Q//fo3H7xm77b5gmYO2/+gMPF33J0D0xveF1X8S25+I5UgRYNqucHJatZ5Z e1CzTWxmM53Y1On+k06B9JOy8dnrT5F75U8h7MvfSY9ZiInJjoKhvDAlc64T6Dag U658zYGThWmQt3zmORFEANYb24YX+VnSuDQysrBqynTXPtBIr/jXnrQiPWBsMToe m1Uo2/QISRegFujlMGaKn6mvPrajFJr9xa3s+83LZV72Lhl7e3ESbba7Kf0wN76M vvtdt6vshc0IknH8SUWDmnyxg9B72TXrVvUkQ9GOdPN+FNdXvMWdMiR2iVWGAA9a EjnOiHFND8qgRqa19j8x95oyRzEicARqSTGW2bC3gAji5+hhCOmz0u5QkxTFYKKd HynJdOTt0p5QsZvyYACLsLVzY6Cx4w8Fc7+q7fq7IVxududHHAHQzLSXVhFT6xpt 5llD4HN10Gizc/xFdL6cGvGQ3nbmh0OMbSCnl4nQfhXHjMLaSuIvDnYImiU5+tY9 mkic1zSeoigF4FtIvnaQ4PjSsq/ypNQnE84I/aUMFBGzBdnyYnvsZHKZvfz7O/nB JZYYzsjxK4MaldOAlyQVlHbIhedJYwv+Fgpq8YZBLwghZMcnsQ1I5uBacEQjUA/5 YN4BiDS12im3l3EmW4fqbo/aSS4PLa7Rkllr3966F4ObQmCtz6Q= =AQ07 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3ficACgkQmmx57+YA GNkzZQ//R5Vf1w4e5iy66snGQ24R/d/zx0lS7+avsbZY1dIfqYdu5mbIXGixv/sC WZ0g00vPF8QmIO+23DLPQIlfwI9Jzqu03KxlnoCxGjtfDz8k1ntJBTCT92+dgtrn FtgPjQf5CFhj+QP4WA5YysQch7Jbxg+PBKtp2YeYJW8UuY2leJJlojgGxNWE8Izu 5z86Ceog8Uu9dKe7zVFoDJNyd8FDxg185OLVbHaOenhYTZKd4lsdpo6N4EDJu/j2 QVmIXdi+kBvzW/RXwJFcEBybP2kQghVISbH0R5Oc+oyUNT/Z52e9HuYHW5b1Hlre NQT8ZJ5hHmM5i7izWSVIyC7cTPRh9VpABzfDQberx+ihWEeGdD6QaPd1UmHTs9Qq 1qdEqmQL5zRCjY/rqL2uUQPN2TfTZvznizCpzUD44CiDQu/zoRV/6CdlZWRBKnDa Z+9iGtyNPzgNyVK96TJ7HZd1Gd8GxxfRJUCako5kHGOdHoft5UBngELvGSPKMwZN RHYNyFphCNmpMvfyL8ZhywyVViTpPYY9LyzKJTZOya5wuQeXjwGuvoszLuaLyHCw aexmDshstEUdf9j6VA/hQcD9lCi14dWQzMdjbNzZrqkVd5BoJDycdHwmqzZOTc/i Xl8rtySU61G8ZHstfTPpSwGrBK2r1PXBBK9xo8t4dKqODxh4IFw= =4UL9 -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Changes for v6.20-rc1 This update improves Device Tree support for 64-bit Tegra platforms, specifically focusing on the Smaug board and the Tegra264 SoC. It enables full USB-C functionality on Smaug by adding role-switching support and enabling DisplayPort altmode. For Tegra264, it introduces nodes for Command Queue Virtualization (CMDQV) in the SMMU, adds the Data Backbone (DBB) clock for the memory controller, and corrects CPU compatible strings to match the Neoverse V3AE core. Additionally, it performs a cleanup by removing redundant status = "okay" properties across Tegra186, Tegra194, Tegra234, and Tegra264 files. * tag 'tegra-for-6.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: smaug: Add usb-role-switch support arm64: tegra: smaug: Complete and enable tegra-udc node arm64: tegra: smaug: Enable DisplayPort via USB-C port arm64: tegra: Correct CPU compatibles on Tegra264 arm64: tegra: Drop unneeded status=okay on Tegra264 arm64: tegra: Drop unneeded status=okay on Tegra234 arm64: tegra: Drop unneeded status=okay on Tegra194 arm64: tegra: Drop unneeded status=okay on Tegra186 arm64: tegra: Add nodes for CMDQV arm64: tegra: Add DBB clock to EMC on Tegra264 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
3d46ce71a7
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@ -120,7 +120,6 @@ gpcdma: dma-controller@2600000 {
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iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
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dma-coherent;
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dma-channel-mask = <0xfffffffe>;
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status = "okay";
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};
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aconnect@2900000 {
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@ -608,7 +607,6 @@ timer@3010000 {
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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uarta: serial@3100000 {
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@ -97,7 +97,6 @@ cbb-noc@2300000 {
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,axi2apb = <&axi2apb>;
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nvidia,apbmisc = <&apbmisc>;
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status = "okay";
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};
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axi2apb: axi2apb@2390000 {
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@ -108,13 +107,11 @@ axi2apb: axi2apb@2390000 {
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<0x0 0x23c0000 0x0 0x1000>,
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<0x0 0x23d0000 0x0 0x1000>,
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<0x0 0x23e0000 0x0 0x1000>;
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status = "okay";
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};
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pinmux: pinmux@2430000 {
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compatible = "nvidia,tegra194-pinmux";
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reg = <0x0 0x2430000 0x0 0x17000>;
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status = "okay";
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pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {
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clkreq {
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@ -208,7 +205,6 @@ gpcdma: dma-controller@2600000 {
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iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
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dma-coherent;
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dma-channel-mask = <0xfffffffe>;
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status = "okay";
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};
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aconnect@2900000 {
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@ -737,7 +733,6 @@ timer@3010000 {
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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uarta: serial@3100000 {
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@ -1359,7 +1354,6 @@ hte_lic: hardware-timestamp@3aa0000 {
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nvidia,int-threshold = <1>;
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nvidia,slices = <11>;
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#timestamp-cells = <1>;
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status = "okay";
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};
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hsp_top0: hsp@3c00000 {
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@ -1547,7 +1541,6 @@ sce-noc@b600000 {
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,axi2apb = <&axi2apb>;
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nvidia,apbmisc = <&apbmisc>;
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status = "okay";
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};
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rce-noc@be00000 {
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@ -1557,7 +1550,6 @@ rce-noc@be00000 {
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,axi2apb = <&axi2apb>;
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nvidia,apbmisc = <&apbmisc>;
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status = "okay";
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};
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hsp_aon: hsp@c150000 {
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@ -1582,7 +1574,6 @@ hte_aon: hardware-timestamp@c1e0000 {
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nvidia,int-threshold = <1>;
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nvidia,slices = <3>;
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#timestamp-cells = <1>;
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status = "okay";
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};
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gen2_i2c: i2c@c240000 {
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@ -1668,8 +1659,6 @@ gpio_aon: gpio@c2f0000 {
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pinmux_aon: pinmux@c300000 {
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compatible = "nvidia,tegra194-pinmux-aon";
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reg = <0x0 0xc300000 0x0 0x4000>;
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status = "okay";
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};
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pwm4: pwm@c340000 {
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@ -1722,7 +1711,6 @@ aon-noc@c600000 {
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interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,apbmisc = <&apbmisc>;
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status = "okay";
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};
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bpmp-noc@d600000 {
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@ -1732,7 +1720,6 @@ bpmp-noc@d600000 {
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,axi2apb = <&axi2apb>;
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nvidia,apbmisc = <&apbmisc>;
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status = "okay";
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};
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iommu@10000000 {
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@ -1886,7 +1873,6 @@ smmu: iommu@12000000 {
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#iommu-cells = <1>;
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nvidia,memory-controller = <&mc>;
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status = "okay";
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};
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host1x@13e00000 {
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@ -3106,7 +3092,6 @@ pmu {
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psci {
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compatible = "arm,psci-1.0";
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status = "okay";
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method = "smc";
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};
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@ -31,6 +31,11 @@ memory@80000000 {
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};
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host1x@50000000 {
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dpaux1: dpaux@54040000 {
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vdd-supply = <&pp3300>;
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status = "okay";
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};
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dsia: dsi@54300000 {
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avdd-dsi-csi-supply = <&vdd_dsi_csi>;
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status = "okay";
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@ -58,6 +63,13 @@ link1: panel@0 {
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};
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};
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sor1: sor@54580000 {
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avdd-io-hdmi-dp-supply = <&pp1800>;
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vdd-hdmi-dp-pll-supply = <&avddio_1v05>;
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nvidia,dpaux = <&dpaux1>;
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status = "okay";
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};
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dpaux: dpaux@545c0000 {
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status = "okay";
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};
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@ -1809,6 +1821,8 @@ usb2-0 {
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status = "okay";
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vbus-supply = <&usbc_vbus>;
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mode = "otg";
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usb-role-switch;
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role-switch-default-mode = "host";
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};
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usb3-0 {
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@ -1843,6 +1857,17 @@ mmc@700b0600 {
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status = "okay";
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};
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usb@700d0000 {
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phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
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<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
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phy-names = "usb2-0", "usb3-0";
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avddio-usb-supply = <&avddio_1v05>;
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hvdd-usb-supply = <&pp3300>;
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status = "okay";
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};
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clock@70110000 {
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status = "okay";
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nvidia,cf = <6>;
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@ -40,7 +40,6 @@ misc@100000 {
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compatible = "nvidia,tegra234-misc";
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reg = <0x0 0x00100000 0x0 0xf000>,
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<0x0 0x0010f000 0x0 0x1000>;
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status = "okay";
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};
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timer@2080000 {
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@ -62,7 +61,6 @@ timer@2080000 {
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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gpio: gpio@2200000 {
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@ -2780,7 +2778,6 @@ mc: memory-controller@2c00000 {
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"ch11", "ch12", "ch13", "ch14", "ch15";
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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#interconnect-cells = <1>;
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status = "okay";
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#address-cells = <2>;
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#size-cells = <2>;
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@ -2812,7 +2809,6 @@ emc: external-memory-controller@2c60000 {
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interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA234_CLK_EMC>;
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clock-names = "emc";
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status = "okay";
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#interconnect-cells = <0>;
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@ -3888,7 +3884,6 @@ smmu_niso1: iommu@8000000 {
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#iommu-cells = <1>;
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nvidia,memory-controller = <&mc>;
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status = "okay";
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};
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sce-fabric@b600000 {
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@ -3902,7 +3897,6 @@ rce-fabric@be00000 {
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compatible = "nvidia,tegra234-rce-fabric";
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reg = <0x0 0xbe00000 0x0 0x40000>;
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interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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hsp_aon: hsp@c150000 {
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@ -4064,28 +4058,24 @@ aon-fabric@c600000 {
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compatible = "nvidia,tegra234-aon-fabric";
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reg = <0x0 0xc600000 0x0 0x40000>;
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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bpmp-fabric@d600000 {
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compatible = "nvidia,tegra234-bpmp-fabric";
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reg = <0x0 0xd600000 0x0 0x40000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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dce-fabric@de00000 {
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compatible = "nvidia,tegra234-dce-fabric";
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reg = <0x0 0xde00000 0x0 0x40000>;
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interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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ccplex@e000000 {
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compatible = "nvidia,tegra234-ccplex-cluster";
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reg = <0x0 0x0e000000 0x0 0x5ffff>;
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nvidia,bpmp = <&bpmp>;
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status = "okay";
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};
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gic: interrupt-controller@f400000 {
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@ -4239,7 +4229,6 @@ smmu_iso: iommu@10000000 {
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#iommu-cells = <1>;
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nvidia,memory-controller = <&mc>;
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status = "okay";
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};
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smmu_niso0: iommu@12000000 {
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@ -4381,14 +4370,12 @@ smmu_niso0: iommu@12000000 {
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#iommu-cells = <1>;
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nvidia,memory-controller = <&mc>;
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status = "okay";
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};
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cbb-fabric@13a00000 {
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compatible = "nvidia,tegra234-cbb-fabric";
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reg = <0x0 0x13a00000 0x0 0x400000>;
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interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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host1x@13e00000 {
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@ -5804,12 +5791,10 @@ dsu-pmu2 {
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pmu {
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compatible = "arm,cortex-a78-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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psci {
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compatible = "arm,psci-1.0";
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status = "okay";
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method = "smc";
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};
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|
|
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@ -23,8 +23,16 @@ iommu@5000000 {
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status = "okay";
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};
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cmdqv@5200000 {
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status = "okay";
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};
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iommu@6000000 {
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status = "okay";
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};
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cmdqv@6200000 {
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status = "okay";
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};
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};
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};
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|
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@ -3361,7 +3361,7 @@ bus@8100000000 {
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<0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
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smmu1: iommu@5000000 {
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compatible = "arm,smmu-v3";
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compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
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reg = <0x00 0x5000000 0x0 0x200000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
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@ -3370,10 +3370,18 @@ smmu1: iommu@5000000 {
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|||
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#iommu-cells = <1>;
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dma-coherent;
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nvidia,cmdqv = <&cmdqv1>;
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||||
};
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cmdqv1: cmdqv@5200000 {
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compatible = "nvidia,tegra264-cmdqv";
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reg = <0x00 0x5200000 0x0 0x830000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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||||
};
|
||||
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smmu2: iommu@6000000 {
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compatible = "arm,smmu-v3";
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compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
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reg = <0x00 0x6000000 0x0 0x200000>;
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||||
interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -3382,6 +3390,14 @@ smmu2: iommu@6000000 {
|
|||
|
||||
#iommu-cells = <1>;
|
||||
dma-coherent;
|
||||
nvidia,cmdqv = <&cmdqv2>;
|
||||
};
|
||||
|
||||
cmdqv2: cmdqv@6200000 {
|
||||
compatible = "nvidia,tegra264-cmdqv";
|
||||
reg = <0x00 0x6200000 0x0 0x830000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mc: memory-controller@8020000 {
|
||||
|
|
@ -3428,8 +3444,9 @@ emc: external-memory-controller@8800000 {
|
|||
reg = <0x00 0x8800000 0x0 0x20000>,
|
||||
<0x00 0x8890000 0x0 0x20000>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA264_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
clocks = <&bpmp TEGRA264_CLK_EMC>,
|
||||
<&bpmp TEGRA264_CLK_DBB_UPHY0>;
|
||||
clock-names = "emc", "dbb";
|
||||
|
||||
#interconnect-cells = <0>;
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
|
|
@ -3437,7 +3454,7 @@ emc: external-memory-controller@8800000 {
|
|||
};
|
||||
|
||||
smmu0: iommu@a000000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
|
||||
reg = <0x00 0xa000000 0x0 0x200000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -3446,10 +3463,18 @@ smmu0: iommu@a000000 {
|
|||
|
||||
#iommu-cells = <1>;
|
||||
dma-coherent;
|
||||
nvidia,cmdqv = <&cmdqv0>;
|
||||
};
|
||||
|
||||
cmdqv0: cmdqv@a200000 {
|
||||
compatible = "nvidia,tegra264-cmdqv";
|
||||
reg = <0x00 0xa200000 0x0 0x830000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smmu4: iommu@b000000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
|
||||
reg = <0x00 0xb000000 0x0 0x200000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -3458,6 +3483,14 @@ smmu4: iommu@b000000 {
|
|||
|
||||
#iommu-cells = <1>;
|
||||
dma-coherent;
|
||||
nvidia,cmdqv = <&cmdqv4>;
|
||||
};
|
||||
|
||||
cmdqv4: cmdqv@b200000 {
|
||||
compatible = "nvidia,tegra264-cmdqv";
|
||||
reg = <0x00 0xb200000 0x0 0x830000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c14: i2c@c410000 {
|
||||
|
|
@ -3690,7 +3723,7 @@ bus@8800000000 {
|
|||
ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
|
||||
|
||||
smmu3: iommu@6000000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
|
||||
reg = <0x00 0x6000000 0x0 0x200000>;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -3699,6 +3732,14 @@ smmu3: iommu@6000000 {
|
|||
|
||||
#iommu-cells = <1>;
|
||||
dma-coherent;
|
||||
nvidia,cmdqv = <&cmdqv3>;
|
||||
};
|
||||
|
||||
cmdqv3: cmdqv@6200000 {
|
||||
compatible = "nvidia,tegra264-cmdqv";
|
||||
reg = <0x00 0x6200000 0x0 0x830000>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hda@90b0000 {
|
||||
|
|
@ -3733,10 +3774,9 @@ cpus {
|
|||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,armv8";
|
||||
compatible = "arm,neoverse-v3ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x00000>;
|
||||
status = "okay";
|
||||
|
||||
enable-method = "psci";
|
||||
|
||||
|
|
@ -3749,10 +3789,9 @@ cpu0: cpu@0 {
|
|||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,armv8";
|
||||
compatible = "arm,neoverse-v3ae";
|
||||
device_type = "cpu";
|
||||
reg = <0x10000>;
|
||||
status = "okay";
|
||||
|
||||
enable-method = "psci";
|
||||
|
||||
|
|
@ -3790,12 +3829,10 @@ thermal {
|
|||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
status = "okay";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
|
|
@ -3822,6 +3859,5 @@ timer {
|
|||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user