arm64: dts: renesas: r9a09g057: Add USB2.0 support

The Renesas RZ/V2H(P) ("R9A09G057") SoC supports 1x channel with OTG/DRD
and 1x channel with host interface.

Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0
channels in R9A09G057 SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515183104.330964-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2025-05-15 19:31:03 +01:00 committed by Geert Uytterhoeven
parent 6aca83a0a8
commit 3cbd627482

View File

@ -807,6 +807,119 @@ gic: interrupt-controller@14900000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
ohci0: usb@15800000 {
compatible = "generic-ohci";
reg = <0 0x15800000 0 0x100>;
interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
resets = <&usb20phyrst>, <&cpg 0xac>;
phys = <&usb2_phy0 1>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
ohci1: usb@15810000 {
compatible = "generic-ohci";
reg = <0 0x15810000 0 0x100>;
interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
resets = <&usb21phyrst>, <&cpg 0xad>;
phys = <&usb2_phy1 1>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
ehci0: usb@15800100 {
compatible = "generic-ehci";
reg = <0 0x15800100 0 0x100>;
interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
resets = <&usb20phyrst>, <&cpg 0xac>;
phys = <&usb2_phy0 2>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&cpg>;
status = "disabled";
};
ehci1: usb@15810100 {
compatible = "generic-ehci";
reg = <0 0x15810100 0 0x100>;
interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
resets = <&usb21phyrst>, <&cpg 0xad>;
phys = <&usb2_phy1 2>;
phy-names = "usb";
companion = <&ohci1>;
power-domains = <&cpg>;
status = "disabled";
};
usb2_phy0: usb-phy@15800200 {
compatible = "renesas,usb2-phy-r9a09g057";
reg = <0 0x15800200 0 0x700>;
interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb3>,
<&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>;
clock-names = "fck", "usb_x1";
resets = <&usb20phyrst>;
#phy-cells = <1>;
power-domains = <&cpg>;
status = "disabled";
};
usb2_phy1: usb-phy@15810200 {
compatible = "renesas,usb2-phy-r9a09g057";
reg = <0 0x15810200 0 0x700>;
interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb4>,
<&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>;
clock-names = "fck", "usb_x1";
resets = <&usb21phyrst>;
#phy-cells = <1>;
power-domains = <&cpg>;
status = "disabled";
};
hsusb: usb@15820000 {
compatible = "renesas,usbhs-r9a09g057",
"renesas,rzg2l-usbhs";
reg = <0 0x15820000 0 0x10000>;
interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
resets = <&usb20phyrst>,
<&cpg 0xae>;
phys = <&usb2_phy0 3>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
usb20phyrst: usb20phy-reset@15830000 {
compatible = "renesas,r9a09g057-usb2phy-reset";
reg = <0 0x15830000 0 0x10000>;
clocks = <&cpg CPG_MOD 0xb6>;
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
status = "disabled";
};
usb21phyrst: usb21phy-reset@15840000 {
compatible = "renesas,r9a09g057-usb2phy-reset";
reg = <0 0x15840000 0 0x10000>;
clocks = <&cpg CPG_MOD 0xb7>;
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
status = "disabled";
};
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;