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arm64: dts: renesas: r9a09g057: Add USB2.0 support
The Renesas RZ/V2H(P) ("R9A09G057") SoC supports 1x channel with OTG/DRD
and 1x channel with host interface.
Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0
channels in R9A09G057 SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515183104.330964-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
parent
6aca83a0a8
commit
3cbd627482
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@ -807,6 +807,119 @@ gic: interrupt-controller@14900000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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ohci0: usb@15800000 {
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compatible = "generic-ohci";
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reg = <0 0x15800000 0 0x100>;
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interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
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resets = <&usb20phyrst>, <&cpg 0xac>;
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phys = <&usb2_phy0 1>;
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phy-names = "usb";
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power-domains = <&cpg>;
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status = "disabled";
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};
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ohci1: usb@15810000 {
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compatible = "generic-ohci";
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reg = <0 0x15810000 0 0x100>;
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interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
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resets = <&usb21phyrst>, <&cpg 0xad>;
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phys = <&usb2_phy1 1>;
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phy-names = "usb";
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power-domains = <&cpg>;
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status = "disabled";
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};
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ehci0: usb@15800100 {
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compatible = "generic-ehci";
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reg = <0 0x15800100 0 0x100>;
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interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
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resets = <&usb20phyrst>, <&cpg 0xac>;
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phys = <&usb2_phy0 2>;
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phy-names = "usb";
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companion = <&ohci0>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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ehci1: usb@15810100 {
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compatible = "generic-ehci";
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reg = <0 0x15810100 0 0x100>;
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interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
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resets = <&usb21phyrst>, <&cpg 0xad>;
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phys = <&usb2_phy1 2>;
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phy-names = "usb";
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companion = <&ohci1>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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usb2_phy0: usb-phy@15800200 {
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compatible = "renesas,usb2-phy-r9a09g057";
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reg = <0 0x15800200 0 0x700>;
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interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb3>,
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<&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>;
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clock-names = "fck", "usb_x1";
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resets = <&usb20phyrst>;
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#phy-cells = <1>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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usb2_phy1: usb-phy@15810200 {
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compatible = "renesas,usb2-phy-r9a09g057";
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reg = <0 0x15810200 0 0x700>;
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interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb4>,
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<&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>;
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clock-names = "fck", "usb_x1";
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resets = <&usb21phyrst>;
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#phy-cells = <1>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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hsusb: usb@15820000 {
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compatible = "renesas,usbhs-r9a09g057",
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"renesas,rzg2l-usbhs";
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reg = <0 0x15820000 0 0x10000>;
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interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
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resets = <&usb20phyrst>,
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<&cpg 0xae>;
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phys = <&usb2_phy0 3>;
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phy-names = "usb";
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power-domains = <&cpg>;
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status = "disabled";
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};
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usb20phyrst: usb20phy-reset@15830000 {
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compatible = "renesas,r9a09g057-usb2phy-reset";
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reg = <0 0x15830000 0 0x10000>;
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clocks = <&cpg CPG_MOD 0xb6>;
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resets = <&cpg 0xaf>;
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power-domains = <&cpg>;
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#reset-cells = <0>;
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status = "disabled";
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};
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usb21phyrst: usb21phy-reset@15840000 {
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compatible = "renesas,r9a09g057-usb2phy-reset";
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reg = <0 0x15840000 0 0x10000>;
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clocks = <&cpg CPG_MOD 0xb7>;
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resets = <&cpg 0xaf>;
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power-domains = <&cpg>;
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#reset-cells = <0>;
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status = "disabled";
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};
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sdhi0: mmc@15c00000 {
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compatible = "renesas,sdhi-r9a09g057";
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reg = <0x0 0x15c00000 0 0x10000>;
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