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wifi: rtw89: Add rtw8851b_dle_mem_usb{2,3}
Add rtw8851b_dle_mem_usb2 and rtw8851b_dle_mem_usb3 and their various quotas and sizes in struct rtw89_mac_size_set. "dle" could be "Data Link Engine" or "Double Link Engine". These are some parameters needed for RTL8851BU. Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/91622304-614e-4e91-bf2f-7688cf44070b@gmail.com
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@ -1645,6 +1645,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* 8852C PCIE SCC */
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.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
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.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
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/* 8852B USB2.0/USB3.0 SCC */
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.wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
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/* PCIE */
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.ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},
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.ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,},
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@ -1660,6 +1662,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
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/* 8852C PCIE SCC */
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.ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
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/* 8852B USB2.0 SCC */
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.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
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/* 8852B USB3.0 SCC */
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.ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
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/* PCIE 64 */
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.wde_qt0 = {3792, 196, 0, 107,},
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.wde_qt0_v1 = {3302, 6, 0, 20,},
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@ -1674,6 +1680,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* 8852C PCIE SCC */
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.wde_qt18 = {3228, 60, 0, 40,},
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.wde_qt23 = {958, 48, 0, 16,},
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/* 8852B USB2.0/USB3.0 SCC */
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.wde_qt25 = {152, 2, 0, 8,},
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.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
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.ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,},
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/* PCIE SCC */
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@ -1697,6 +1705,13 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* PCIE 64 */
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.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
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.ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,},
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/* USB2.0 52B SCC */
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.ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,},
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/* USB2.0 52B 92K */
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.ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,},
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/* USB3.0 52B 92K */
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.ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
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.ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
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/* 8852A PCIE WOW */
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.ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
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/* 8852B PCIE WOW */
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@ -924,6 +924,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size wde_size18;
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const struct rtw89_dle_size wde_size19;
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const struct rtw89_dle_size wde_size23;
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const struct rtw89_dle_size wde_size25;
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const struct rtw89_dle_size ple_size0;
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const struct rtw89_dle_size ple_size0_v1;
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const struct rtw89_dle_size ple_size3_v1;
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@ -933,6 +934,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size ple_size9;
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const struct rtw89_dle_size ple_size18;
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const struct rtw89_dle_size ple_size19;
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const struct rtw89_dle_size ple_size32;
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const struct rtw89_dle_size ple_size33;
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const struct rtw89_wde_quota wde_qt0;
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const struct rtw89_wde_quota wde_qt0_v1;
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const struct rtw89_wde_quota wde_qt4;
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@ -941,6 +944,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_wde_quota wde_qt17;
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const struct rtw89_wde_quota wde_qt18;
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const struct rtw89_wde_quota wde_qt23;
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const struct rtw89_wde_quota wde_qt25;
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const struct rtw89_ple_quota ple_qt0;
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const struct rtw89_ple_quota ple_qt1;
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const struct rtw89_ple_quota ple_qt4;
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@ -955,6 +959,10 @@ struct rtw89_mac_size_set {
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const struct rtw89_ple_quota ple_qt57;
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const struct rtw89_ple_quota ple_qt58;
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const struct rtw89_ple_quota ple_qt59;
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const struct rtw89_ple_quota ple_qt72;
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const struct rtw89_ple_quota ple_qt73;
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const struct rtw89_ple_quota ple_qt74;
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const struct rtw89_ple_quota ple_qt75;
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const struct rtw89_ple_quota ple_qt_52a_wow;
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const struct rtw89_ple_quota ple_qt_52b_wow;
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const struct rtw89_ple_quota ple_qt_52bt_wow;
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@ -68,6 +68,32 @@ static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
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NULL},
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};
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static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
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&rtw89_mac_size.ple_size32, &rtw89_mac_size.wde_qt25,
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&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt72,
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&rtw89_mac_size.ple_qt73},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
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&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
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&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
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&rtw89_mac_size.ple_qt13},
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[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
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NULL},
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};
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static const struct rtw89_dle_mem rtw8851b_dle_mem_usb3[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
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&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
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&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
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&rtw89_mac_size.ple_qt75},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
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&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
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&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
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&rtw89_mac_size.ple_qt13},
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[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
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NULL},
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};
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static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
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{0x46D0, GENMASK(1, 0), 0x3},
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{0x4AD4, GENMASK(31, 0), 0xf},
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@ -2509,7 +2535,10 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
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.dis_2g_40m_ul_ofdma = true,
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.rsvd_ple_ofst = 0x2f800,
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.hfc_param_ini = {rtw8851b_hfc_param_ini_pcie, NULL, NULL},
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.dle_mem = {rtw8851b_dle_mem_pcie, NULL, NULL, NULL},
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.dle_mem = {rtw8851b_dle_mem_pcie,
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rtw8851b_dle_mem_usb2,
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rtw8851b_dle_mem_usb3,
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NULL},
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.wde_qempty_acq_grpnum = 4,
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.wde_qempty_mgq_grpsel = 4,
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.rf_base_addr = {0xe000},
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