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rk3399 vdu clock-rate fix, otg port fix on Quartz64-A and ethernet

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fix on Quartz64-B (actual production model)
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Merge tag 'v5.19-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes

rk3399 vdu clock-rate fix, otg port fix on Quartz64-A and ethernet
fix on Quartz64-B (actual production model)

* tag 'v5.19-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Assign RK3399 VDU clock rate
  arm64: dts: rockchip: Fix Quartz64-A dwc3 otg port behavior
  arm64: dts: rockchip: Fix ethernet on production Quartz64-B

Link: https://lore.kernel.org/r/7723415.29KlJPOoH8@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-07-06 13:35:12 +02:00
commit 3c5a4e6d83
4 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
View File

@ -376,7 +376,8 @@ &cru {
<&cru ACLK_VIO>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>,
<&cru ACLK_HDCP>;
<&cru ACLK_HDCP>,
<&cru ACLK_VDU>;
assigned-clock-rates =
<600000000>, <1600000000>,
<1000000000>,
@ -388,6 +389,7 @@ &cru {
<400000000>,
<200000000>,
<200000000>,
<400000000>,
<400000000>;
};

6
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -1462,7 +1462,8 @@ cru: clock-controller@ff760000 {
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
<&cru PCLK_DDR>,
<&cru ACLK_VDU>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@ -1473,7 +1474,8 @@ cru: clock-controller@ff760000 {
<100000000>, <50000000>,
<400000000>, <400000000>,
<200000000>,
<200000000>;
<200000000>,
<400000000>;
};
grf: syscon@ff770000 {

1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
View File

@ -687,6 +687,7 @@ &usb_host1_ohci {
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
View File

@ -133,7 +133,7 @@ &gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
clock_in_out = "input";
phy-mode = "rgmii-id";
phy-mode = "rgmii";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim