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arm64: dts: qcom: sa8775p: Add PCIe bridge node

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On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2024-03-21 16:46:28 +05:30 committed by Bjorn Andersson
parent cf3e010d7f
commit 3c3abb944d
1 changed files with 20 additions and 0 deletions
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20
arch/arm64/boot/dts/qcom/sa8775p.dtsi
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@ -3677,6 +3677,16 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_phy: phy@1c04000 {
@ -3777,6 +3787,16 @@ pcie1: pcie@1c10000 {
phy-names = "pciephy";
status = "disabled";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie1_phy: phy@1c14000 {