mirror of
https://github.com/torvalds/linux.git
synced 2026-05-25 15:41:52 +02:00
drm/amdgpu: retire ip init code specific for A0 rev
For aqua_vanjaram, A0 HW is retired so remove the code specific for it in gfx ip init. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
334dc5fcc3
commit
3bc7bc73af
|
|
@ -349,18 +349,7 @@ static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
|
|||
|
||||
WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
|
||||
GOLDEN_GB_ADDR_CONFIG);
|
||||
if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) {
|
||||
WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1);
|
||||
} else {
|
||||
/* Golden settings applied by driver for ASIC with rev_id 0 */
|
||||
if (adev->rev_id == 0) {
|
||||
WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
|
||||
REDUCE_FIFO_DEPTH_BY_2, 2);
|
||||
} else {
|
||||
WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,
|
||||
SPARE, 0x1);
|
||||
}
|
||||
}
|
||||
WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user