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dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"

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[ Upstream commit c24a5c735f ]

The commit

  080edf75d3 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")

has been mistakenly submitted. The further investigations show that
the original code does better job since the memory side transfer size
has never been configured by DMA users.

As per latest revision of documentation: "Channel minimum transfer size
(CHnMTSR)... For IOSF UART, maximum value that can be programmed is 64 and
minimum value that can be programmed is 1."

This reverts commit 080edf75d3.

Fixes: 080edf75d3 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Andy Shevchenko 2019-06-13 16:32:32 +03:00 committed by Greg Kroah-Hartman
parent 574fe4c9a3
commit 3b8e3cf692
1 changed files with 2 additions and 2 deletions
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4
drivers/dma/hsu/hsu.c
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@ -64,10 +64,10 @@ static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
if (hsuc->direction == DMA_MEM_TO_DEV) {
bsr = config->dst_maxburst;
mtsr = config->src_addr_width;
mtsr = config->dst_addr_width;
} else if (hsuc->direction == DMA_DEV_TO_MEM) {
bsr = config->src_maxburst;
mtsr = config->dst_addr_width;
mtsr = config->src_addr_width;
}
hsu_chan_disable(hsuc);