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phy: lynx-28g: use FIELD_GET() and FIELD_PREP()
Reduce the number of bit field definitions required in this driver (in the worst case, a read form and a write form), by defining just the mask, and using the FIELD_GET() and FIELD_PREP() API from <linux/bitfield.h> with that. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20251125114847.804961-8-vladimir.oltean@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Vladimir Oltean
Vinod Koul
parent
6e3d3e8783
commit
3b84377c2a
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (c) 2021-2022 NXP. */
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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@ -29,26 +30,26 @@
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#define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
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#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
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#define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
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#define PLLnCR0_REFCLK_SEL GENMASK(20, 16)
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#define PLLnCR0_REFCLK_SEL_100MHZ 0x0
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#define PLLnCR0_REFCLK_SEL_125MHZ 0x10000
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#define PLLnCR0_REFCLK_SEL_156MHZ 0x20000
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#define PLLnCR0_REFCLK_SEL_150MHZ 0x30000
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#define PLLnCR0_REFCLK_SEL_161MHZ 0x40000
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#define PLLnCR0_REFCLK_SEL_125MHZ 0x1
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#define PLLnCR0_REFCLK_SEL_156MHZ 0x2
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#define PLLnCR0_REFCLK_SEL_150MHZ 0x3
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#define PLLnCR0_REFCLK_SEL_161MHZ 0x4
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#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
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#define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
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#define PLLnCR1_FRATE_SEL GENMASK(28, 24)
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#define PLLnCR1_FRATE_5G_10GVCO 0x0
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#define PLLnCR1_FRATE_5G_25GVCO 0x10000000
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#define PLLnCR1_FRATE_10G_20GVCO 0x6000000
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#define PLLnCR1_FRATE_5G_25GVCO 0x10
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#define PLLnCR1_FRATE_10G_20GVCO 0x6
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/* Per SerDes lane registers */
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/* Lane a General Control Register */
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#define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
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#define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
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#define LNaGCR0_PROTO_SEL_SGMII 0x8
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#define LNaGCR0_PROTO_SEL_XFI 0x50
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#define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
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#define LNaGCR0_PROTO_SEL GENMASK(7, 3)
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#define LNaGCR0_PROTO_SEL_SGMII 0x1
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#define LNaGCR0_PROTO_SEL_XFI 0xa
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#define LNaGCR0_IF_WIDTH GENMASK(2, 0)
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#define LNaGCR0_IF_WIDTH_10_BIT 0x0
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#define LNaGCR0_IF_WIDTH_20_BIT 0x2
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@ -60,13 +61,13 @@
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/* Lane a Tx General Control Register */
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#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
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#define LNaTGCR0_USE_PLL BIT(28)
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#define LNaTGCR0_USE_PLLF 0x0
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#define LNaTGCR0_USE_PLLS BIT(28)
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#define LNaTGCR0_USE_PLL_MSK BIT(28)
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#define LNaTGCR0_USE_PLLS 0x1
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#define LNaTGCR0_N_RATE GENMASK(26, 24)
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#define LNaTGCR0_N_RATE_FULL 0x0
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#define LNaTGCR0_N_RATE_HALF 0x1000000
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#define LNaTGCR0_N_RATE_QUARTER 0x2000000
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#define LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LNaTGCR0_N_RATE_HALF 0x1
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#define LNaTGCR0_N_RATE_QUARTER 0x2
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#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
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@ -79,14 +80,13 @@
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/* Lane a Rx General Control Register */
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#define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
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#define LNaRGCR0_USE_PLL BIT(28)
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#define LNaRGCR0_USE_PLLF 0x0
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#define LNaRGCR0_USE_PLLS BIT(28)
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#define LNaRGCR0_USE_PLL_MSK BIT(28)
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#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LNaRGCR0_USE_PLLS 0x1
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#define LNaRGCR0_N_RATE GENMASK(26, 24)
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#define LNaRGCR0_N_RATE_FULL 0x0
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#define LNaRGCR0_N_RATE_HALF 0x1000000
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#define LNaRGCR0_N_RATE_QUARTER 0x2000000
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#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
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#define LNaRGCR0_N_RATE_HALF 0x1
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#define LNaRGCR0_N_RATE_QUARTER 0x2
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#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
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@ -97,13 +97,12 @@
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#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
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#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
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#define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
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#define LNaPSS_TYPE GENMASK(30, 24)
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#define LNaPSS_TYPE_SGMII 0x4
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#define LNaPSS_TYPE_XFI 0x28
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#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
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#define SGMIIaCR1_SGPCS_EN BIT(11)
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#define SGMIIaCR1_SGPCS_MSK BIT(11)
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struct lynx_28g_priv;
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@ -197,18 +196,18 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
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struct lynx_28g_pll *pll,
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phy_interface_t intf)
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{
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switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
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switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
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case PLLnCR1_FRATE_5G_10GVCO:
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case PLLnCR1_FRATE_5G_25GVCO:
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switch (intf) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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lynx_28g_lane_rmw(lane, LNaTGCR0,
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LNaTGCR0_N_RATE_QUARTER,
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LNaTGCR0_N_RATE_MSK);
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FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_QUARTER),
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LNaTGCR0_N_RATE);
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lynx_28g_lane_rmw(lane, LNaRGCR0,
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LNaRGCR0_N_RATE_QUARTER,
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LNaRGCR0_N_RATE_MSK);
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FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_QUARTER),
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LNaRGCR0_N_RATE);
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break;
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default:
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break;
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@ -218,10 +217,12 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
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switch (intf) {
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_USXGMII:
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lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_N_RATE_FULL,
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LNaTGCR0_N_RATE_MSK);
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lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_N_RATE_FULL,
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LNaRGCR0_N_RATE_MSK);
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lynx_28g_lane_rmw(lane, LNaTGCR0,
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FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_FULL),
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LNaTGCR0_N_RATE);
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lynx_28g_lane_rmw(lane, LNaRGCR0,
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FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_FULL),
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LNaRGCR0_N_RATE);
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break;
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default:
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break;
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@ -236,15 +237,19 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
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struct lynx_28g_pll *pll)
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{
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if (pll->id == 0) {
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lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLF,
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LNaTGCR0_USE_PLL_MSK);
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lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLF,
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LNaRGCR0_USE_PLL_MSK);
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lynx_28g_lane_rmw(lane, LNaTGCR0,
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FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLF),
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LNaTGCR0_USE_PLL);
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lynx_28g_lane_rmw(lane, LNaRGCR0,
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FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLF),
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LNaRGCR0_USE_PLL);
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} else {
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lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLS,
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LNaTGCR0_USE_PLL_MSK);
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lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLS,
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LNaRGCR0_USE_PLL_MSK);
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lynx_28g_lane_rmw(lane, LNaTGCR0,
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FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLS),
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LNaTGCR0_USE_PLL);
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lynx_28g_lane_rmw(lane, LNaRGCR0,
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FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLS),
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LNaRGCR0_USE_PLL);
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}
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}
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@ -286,8 +291,9 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
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/* Setup the protocol select and SerDes parallel interface width */
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lynx_28g_lane_rmw(lane, LNaGCR0,
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LNaGCR0_PROTO_SEL_SGMII | LNaGCR0_IF_WIDTH_10_BIT,
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LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
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FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_SGMII) |
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FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_10_BIT),
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LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
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/* Find the PLL that works with this interface type */
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pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
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@ -302,7 +308,7 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
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/* Enable the SGMII PCS */
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lynx_28g_lane_rmw(lane, SGMIIaCR1, SGMIIaCR1_SGPCS_EN,
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SGMIIaCR1_SGPCS_MSK);
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SGMIIaCR1_SGPCS_EN);
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/* Configure the appropriate equalization parameters for the protocol */
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iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
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@ -328,8 +334,9 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
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/* Setup the protocol select and SerDes parallel interface width */
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lynx_28g_lane_rmw(lane, LNaGCR0,
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LNaGCR0_PROTO_SEL_XFI | LNaGCR0_IF_WIDTH_20_BIT,
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LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
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FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_XFI) |
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FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_20_BIT),
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LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
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/* Find the PLL that works with this interface type */
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pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
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@ -343,7 +350,7 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
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lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
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/* Disable the SGMII PCS */
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lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_MSK);
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lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
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/* Configure the appropriate equalization parameters for the protocol */
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iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
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@ -513,7 +520,7 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
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if (PLLnRSTCTL_DIS(pll->rstctl))
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continue;
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switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
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switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
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case PLLnCR1_FRATE_5G_10GVCO:
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case PLLnCR1_FRATE_5G_25GVCO:
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/* 5GHz clock net */
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@ -570,7 +577,7 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
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u32 pss, protocol;
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pss = lynx_28g_lane_read(lane, LNaPSS);
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protocol = LNaPSS_TYPE(pss);
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protocol = FIELD_GET(LNaPSS_TYPE, pss);
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switch (protocol) {
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case LNaPSS_TYPE_SGMII:
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lane->interface = PHY_INTERFACE_MODE_SGMII;
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