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drm/amd/pm: Replace without wait with async calls

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Use the new async locked message function instead of without_waiting
messaging function.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2025-12-16 12:55:26 +05:30 committed by Alex Deucher
parent c42852d83d
commit 3b77437019
7 changed files with 64 additions and 59 deletions
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22
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -3043,21 +3043,21 @@ static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
static int sienna_cichlid_mode2_reset(struct smu_context *smu)
{
int ret = 0, index;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
struct amdgpu_device *adev = smu->adev;
int ret = 0;
int timeout = 100;
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_DriverMode2Reset);
mutex_lock(&ctl->lock);
mutex_lock(&smu->message_lock);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_DriverMode2Reset,
SMU_RESET_MODE_2);
if (ret)
goto out;
ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
SMU_RESET_MODE_2);
ret = smu_cmn_wait_for_response(smu);
ret = smu_msg_wait_response(ctl, 0);
while (ret != 0 && timeout) {
ret = smu_cmn_wait_for_response(smu);
ret = smu_msg_wait_response(ctl, 0);
/* Wait a bit more time for getting ACK */
if (ret != 0) {
--timeout;
@ -3075,11 +3075,11 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu)
goto out;
}
dev_info(smu->adev->dev, "restore config space...\n");
dev_info(adev->dev, "restore config space...\n");
/* Restore the config space saved during init */
amdgpu_device_load_pci_state(adev->pdev);
out:
mutex_unlock(&smu->message_lock);
mutex_unlock(&ctl->lock);
return ret;
}

16
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
View File

@ -2272,18 +2272,12 @@ static int vangogh_post_smu_init(struct smu_context *smu)
static int vangogh_mode_reset(struct smu_context *smu, int type)
{
int ret = 0, index = 0;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
int ret;
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_GfxDeviceDriverReset);
if (index < 0)
return index == -EACCES ? 0 : index;
mutex_lock(&smu->message_lock);
ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
mutex_unlock(&smu->message_lock);
mutex_lock(&ctl->lock);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, type);
mutex_unlock(&ctl->lock);
mdelay(10);

24
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
View File

@ -1828,26 +1828,28 @@ static int aldebaran_mode1_reset(struct smu_context *smu)
static int aldebaran_mode2_reset(struct smu_context *smu)
{
int ret = 0, index;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
struct amdgpu_device *adev = smu->adev;
int ret = 0;
int timeout = 10;
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_GfxDeviceDriverReset);
if (index < 0 )
return -EINVAL;
mutex_lock(&smu->message_lock);
mutex_lock(&ctl->lock);
if (smu->smc_fw_version >= 0x00441400) {
ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset,
SMU_RESET_MODE_2);
if (ret)
goto out;
/* This is similar to FLR, wait till max FLR timeout */
msleep(100);
dev_dbg(smu->adev->dev, "restore config space...\n");
dev_dbg(adev->dev, "restore config space...\n");
/* Restore the config space saved during init */
amdgpu_device_load_pci_state(adev->pdev);
dev_dbg(smu->adev->dev, "wait for reset ack\n");
dev_dbg(adev->dev, "wait for reset ack\n");
while (ret == -ETIME && timeout) {
ret = smu_cmn_wait_for_response(smu);
ret = smu_msg_wait_response(ctl, 0);
/* Wait a bit more time for getting ACK */
if (ret == -ETIME) {
--timeout;
@ -1870,7 +1872,7 @@ static int aldebaran_mode2_reset(struct smu_context *smu)
if (ret == 1)
ret = 0;
out:
mutex_unlock(&smu->message_lock);
mutex_unlock(&ctl->lock);
return ret;
}

13
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
View File

@ -2244,18 +2244,21 @@ int smu_v13_0_baco_exit(struct smu_context *smu)
int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
{
uint16_t index;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
struct amdgpu_device *adev = smu->adev;
int ret;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
}
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_EnableGfxImu);
return smu_cmn_send_msg_without_waiting(smu, index,
ENABLE_IMU_ARG_GFXOFF_ENABLE);
mutex_lock(&ctl->lock);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu,
ENABLE_IMU_ARG_GFXOFF_ENABLE);
mutex_unlock(&ctl->lock);
return ret;
}
int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,

24
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
View File

@ -2897,24 +2897,22 @@ static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
{
int ret = 0, index;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
struct amdgpu_device *adev = smu->adev;
int ret = 0;
int timeout = 10;
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_GfxDeviceDriverReset);
if (index < 0)
return index;
mutex_lock(&ctl->lock);
mutex_lock(&smu->message_lock);
ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
SMU_RESET_MODE_2);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset,
SMU_RESET_MODE_2);
if (ret)
goto out;
/* Reset takes a bit longer, wait for 200ms. */
msleep(200);
dev_dbg(smu->adev->dev, "restore config space...\n");
dev_dbg(adev->dev, "restore config space...\n");
/* Restore the config space saved during init */
amdgpu_device_load_pci_state(adev->pdev);
@ -2932,9 +2930,9 @@ static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
if (!(adev->flags & AMD_IS_APU))
smu_v13_0_6_restore_pci_config(smu);
dev_dbg(smu->adev->dev, "wait for reset ack\n");
dev_dbg(adev->dev, "wait for reset ack\n");
do {
ret = smu_cmn_wait_for_response(smu);
ret = smu_msg_wait_response(ctl, 0);
/* Wait a bit more time for getting ACK */
if (ret == -ETIME) {
--timeout;
@ -2948,7 +2946,7 @@ static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
} while (ret == -ETIME && timeout);
out:
mutex_unlock(&smu->message_lock);
mutex_unlock(&ctl->lock);
if (ret)
dev_err(adev->dev, "failed to send mode2 reset, error code %d",

12
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
View File

@ -1834,17 +1834,21 @@ int smu_v14_0_baco_exit(struct smu_context *smu)
int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
{
uint16_t index;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
struct amdgpu_device *adev = smu->adev;
int ret;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
}
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_EnableGfxImu);
return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE);
mutex_lock(&ctl->lock);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu,
ENABLE_IMU_ARG_GFXOFF_ENABLE);
mutex_unlock(&ctl->lock);
return ret;
}
int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)

12
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
View File

@ -1709,17 +1709,21 @@ int smu_v15_0_baco_exit(struct smu_context *smu)
int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu)
{
uint16_t index;
struct smu_msg_ctl *ctl = &smu->msg_ctl;
struct amdgpu_device *adev = smu->adev;
int ret;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
}
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
SMU_MSG_EnableGfxImu);
return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE);
mutex_lock(&ctl->lock);
ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu,
ENABLE_IMU_ARG_GFXOFF_ENABLE);
mutex_unlock(&ctl->lock);
return ret;
}
int smu_v15_0_set_default_dpm_tables(struct smu_context *smu)