From 2c53c272d0d8757e506b16b3c291c5ec193c8ef5 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 22 Jan 2015 11:07:00 +0100 Subject: [PATCH 1/8] ARM: sti: Provide DT nodes for SSC[0..4] The Synchronous Serial Controller is used to provide SPI. Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index c06a54681912..9eba0dc59b42 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -336,5 +336,59 @@ phy_port2: port@8f95000 { resets = <&softreset STIH407_MIPHY2_SOFTRESET>; }; }; + + spi@9840000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9840000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-0 = <&pinctrl_spi0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9841000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9841000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9842000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9842000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9843000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9843000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9844000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9844000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; }; }; From b0bb2bae194f17cdc8d455c1d4503bc3bf733897 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 22 Jan 2015 11:07:00 +0100 Subject: [PATCH 2/8] ARM: sti: Provide DT nodes for SBC SSC[0..2] The Synchronous Serial Controller is used to provide SPI. These are the ports which are located on the Stand-By Controller (SBC). Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 9eba0dc59b42..655f8544a673 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -390,5 +390,36 @@ spi@9844000 { status = "disabled"; }; + + /* SBC SSC */ + spi@9540000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9540000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9541000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9541000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9542000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9542000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + + status = "disabled"; + }; }; }; From 9286ac4829ba66efa1c258411dfe51736cb3cfc0 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 10 Apr 2015 11:40:00 +0200 Subject: [PATCH 3/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc. The nodes have been split to allow as much commonality as possible. The stih407 has a silicon bug with eMMC UHS modes (with top regs) and as such doesn't have any of the uhs dt properties. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 30 +++++++++++++++++++++++++++ arch/arm/boot/dts/stih410-b2120.dts | 10 +++++++++ arch/arm/boot/dts/stihxxx-b2120.dtsi | 8 +++++++ 3 files changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 655f8544a673..11d5c70b8d80 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -421,5 +421,35 @@ spi@9542000 { status = "disabled"; }; + + mmc0: sdhci@09060000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + status = "disabled"; + reg = <0x09060000 0x7ff>, <0x9061008 0x20>; + reg-names = "mmc", "top-mmc-delay"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_c0_flexgen CLK_MMC_0>; + bus-width = <8>; + non-removable; + }; + + mmc1: sdhci@09080000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + status = "disabled"; + reg = <0x09080000 0x7ff>; + reg-names = "mmc"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + clock-names = "mmc"; + clocks = <&clk_s_c0_flexgen CLK_MMC_1>; + resets = <&softreset STIH407_MMC1_SOFTRESET>; + bus-width = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 2f61a9960dee..16f02c5e33a4 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -26,4 +26,14 @@ memory { aliases { ttyAS0 = &sbc_serial0; }; + + soc { + + mmc0: sdhci@09060000 { + max-frequency = <200000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + }; + }; }; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index c1d859092be7..64fa0b5a0f24 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -47,6 +47,14 @@ i2c@9540000 { status = "okay"; }; + mmc0: sdhci@09060000 { + status = "okay"; + }; + + mmc1: sdhci@09080000 { + status = "okay"; + }; + /* SSC11 to HDMI */ hdmiddc: i2c@9541000 { status = "okay"; From ba7f2728dd6f266a8b46def8eb7ede07a2ed2b00 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 10 Apr 2015 11:40:00 +0200 Subject: [PATCH 4/8] ARM: STi: DT: STiH418: Add dt nodes for sdhci and emmc. Add dt nodes to enable sdhci / eMMC for stih418-b2199 board. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih418-b2199.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 926235c08e4d..a2fdada5b4e5 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -74,5 +74,17 @@ i2c@9541000 { st,i2c-min-scl-pulse-width-us = <0>; st,i2c-min-sda-pulse-width-us = <5>; }; + + mmc1: sdhci@09080000 { + status = "okay"; + }; + + mmc0: sdhci@09060000 { + status = "okay"; + max-frequency = <200000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + }; }; }; From 0b30d25d08ab2033fd6e7fced7fa0d77f9eaa7de Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 9 Apr 2015 15:47:26 +0100 Subject: [PATCH 5/8] mfd: dt-bindings: Provide human readable defines for LPC mode choosing ST's Low Power Controller can currently operate in two supported modes; Watchdog and Real Time Clock. These defines will aid engineers to easily identify the selected mode. Reviewed-by: Guenter Roeck Acked-by: Maxime Coquelin Signed-off-by: Lee Jones --- include/dt-bindings/mfd/st-lpc.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/mfd/st-lpc.h diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h new file mode 100644 index 000000000000..e3e6c75d8822 --- /dev/null +++ b/include/dt-bindings/mfd/st-lpc.h @@ -0,0 +1,15 @@ +/* + * This header provides shared DT/Driver defines for ST's LPC device + * + * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved + * + * Author: Lee Jones for STMicroelectronics + */ + +#ifndef __DT_BINDINGS_ST_LPC_H__ +#define __DT_BINDINGS_ST_LPC_H__ + +#define ST_LPC_MODE_RTC 0 +#define ST_LPC_MODE_WDT 1 + +#endif /* __DT_BINDINGS_ST_LPC_H__ */ From 358764f306242bf2b3d71693b04b05e0b75718ae Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 9 Apr 2015 16:47:00 +0200 Subject: [PATCH 6/8] ARM: STi: DT: STiH407: Add Device Tree node for the LPC On current ST platforms the LPC controls a number of functions. This patch enables support for the LPC Watchdog and LPC RTC devices on LPC1 and LPC2 respectively. Signed-off-by: David Paris Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 11d5c70b8d80..cdee4a7799b4 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -7,6 +7,7 @@ * publishhed by the Free Software Foundation. */ #include "stih407-pinctrl.dtsi" +#include #include / { #address-cells = <1>; @@ -451,5 +452,24 @@ mmc1: sdhci@09080000 { resets = <&softreset STIH407_MMC1_SOFTRESET>; bus-width = <4>; }; + + /* Watchdog and Real-Time Clock */ + lpc@8787000 { + compatible = "st,stih407-lpc"; + reg = <0x8787000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + timeout-sec = <120>; + st,syscfg = <&syscfg_core>; + st,lpc-mode = ; + }; + + lpc@8788000 { + compatible = "st,stih407-lpc"; + reg = <0x8788000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_1>; + st,lpc-mode = ; + }; }; }; From d90accb913a7a72172ec6b82f8b8766d9c9bf8bf Mon Sep 17 00:00:00 2001 From: Karim BEN BELGACEM Date: Wed, 18 Mar 2015 18:21:00 +0100 Subject: [PATCH 7/8] ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35 This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM Acked-by: Maxime Coquelin Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 402844cb3152..0a754f275212 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -104,6 +104,7 @@ pio5: gpio@09615000 { #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO5"; + st,retime-pin-mask = <0x3f>; }; rc { @@ -519,6 +520,7 @@ pio35: gpio@09225000 { #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO35"; + st,retime-pin-mask = <0x7f>; }; i2c4 { From b3d37f92a79a329c392712da5e71fdd6c0258c3a Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 31 Mar 2015 09:35:00 +0200 Subject: [PATCH 8/8] ARM: DT: STi: STiH407: Add sata DT nodes. Now that the miphy28lp is upstream, we can add the sata dt nodes for stih407 family silicon. This has been tested on b2120 board J4 (sata0 channel). These nodes are disabled by default as a special mini pci-e to sata daughter board is required which isn't shipped with the board. Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index cdee4a7799b4..85159b823867 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -8,6 +8,7 @@ */ #include "stih407-pinctrl.dtsi" #include +#include #include / { #address-cells = <1>; @@ -471,5 +472,49 @@ lpc@8788000 { clocks = <&clk_s_d3_flexgen CLK_LPC_1>; st,lpc-mode = ; }; + + sata0: sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + + sata1: sata@9b28000 { + compatible = "st,ahci"; + reg = <0x9b28000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port1 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA1_POWERDOWN>, + <&softreset STIH407_SATA1_SOFTRESET>, + <&softreset STIH407_SATA1_PWR_SOFTRESET>; + reset-names = "pwr-dwn", + "sw-rst", + "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; }; };