Merge "dt-bindings: interconnect: Add endpoint IDs for Pineapple"

2026-07-30 19:21:28 +02:00 · 2022-05-26 23:01:34 -07:00 · 2022-05-26 23:01:34 -07:00 · 3b02cc73f3
commit 3b02cc73f3
parent 9b66754069 64974c3bcd
4 changed files with 306 additions and 0 deletions
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@ -11,6 +11,16 @@ menuconfig INTERCONNECT

 if INTERCONNECT

+menuconfig INTERCONNECT_TEST
+	tristate "Debugfs test"
+	depends on DEBUG_FS
+	help
+	  Expose the interconnect API to userspace for testing purposes. This
+	  will create /sys/kernel/debug/interconnect-test to allow requesting
+	  bandwidth between endpoints.
+
+	  If unsure, say no.
+
 source "drivers/interconnect/imx/Kconfig"
 source "drivers/interconnect/qcom/Kconfig"
 source "drivers/interconnect/samsung/Kconfig"
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@ -2,8 +2,10 @@

 CFLAGS_core.o				:= -I$(src)
 icc-core-objs				:= core.o bulk.o
+icc-test-objs				:= debugfs-test.o

 obj-$(CONFIG_INTERCONNECT)		+= icc-core.o
+obj-$(CONFIG_INTERCONNECT_TEST)		+= icc-test.o
 obj-$(CONFIG_INTERCONNECT_IMX)		+= imx/
 obj-$(CONFIG_INTERCONNECT_QCOM)		+= qcom/
 obj-$(CONFIG_INTERCONNECT_SAMSUNG)	+= samsung/
--- a/drivers/interconnect/debugfs-test.c
+++ b/drivers/interconnect/debugfs-test.c
@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017, Linaro Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/interconnect.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+
+static struct platform_device *icc_pdev;
+static struct dentry *debugfs_dir;
+static struct icc_path *path;
+static u32 src_port;
+static u32 dst_port;
+
+static u32 avg_bw;
+static u32 peak_bw;
+
+static ssize_t get_write_op(struct file *file, char const __user *buf,
+			    size_t count, loff_t *ppos)
+{
+	unsigned long val;
+	int ret;
+
+	ret = kstrtoul_from_user(buf, count, 10, &val);
+	if (ret)
+		return ret;
+
+	path = icc_get(&icc_pdev->dev, src_port, dst_port);
+	if (IS_ERR(path))
+		return PTR_ERR(path);
+
+	*ppos += count;
+
+	return count;
+}
+
+static const struct file_operations get_fops = {
+	.owner = THIS_MODULE,
+	.write = get_write_op
+};
+
+static ssize_t commit_write_op(struct file *file, char const __user *buf,
+			       size_t count, loff_t *ppos)
+{
+	unsigned long val;
+	int ret;
+
+	ret = kstrtoul_from_user(buf, count, 10, &val);
+	if (ret)
+		return ret;
+
+	if (IS_ERR(path))
+		return PTR_ERR(path);
+
+	ret = icc_set_bw(path, avg_bw, peak_bw);
+	if (ret)
+		return ret;
+
+	*ppos += count;
+
+	return count;
+}
+
+static const struct file_operations commit_fops = {
+	.owner = THIS_MODULE,
+	.write = commit_write_op
+};
+
+static void __exit icc_test_exit(void)
+{
+	if (!IS_ERR(path))
+		icc_put(path);
+
+	debugfs_remove_recursive(debugfs_dir);
+	platform_device_del(icc_pdev);
+	platform_device_put(icc_pdev);
+}
+
+static int __init icc_test_init(void)
+{
+	icc_pdev = platform_device_alloc("icc-test", PLATFORM_DEVID_AUTO);
+	platform_device_add(icc_pdev);
+
+	debugfs_dir = debugfs_create_dir("interconnect-test", NULL);
+	if (!debugfs_dir)
+		pr_err("interconnect: error creating debugfs directory\n");
+
+	debugfs_create_u32("src_port", 0600, debugfs_dir, &src_port);
+	debugfs_create_u32("dst_port", 0600, debugfs_dir, &dst_port);
+	debugfs_create_file("get", 0200, debugfs_dir, NULL, &get_fops);
+	debugfs_create_u32("avg_bw", 0600, debugfs_dir, &avg_bw);
+	debugfs_create_u32("peak_bw", 0600, debugfs_dir, &peak_bw);
+	debugfs_create_file("commit", 0200, debugfs_dir, NULL, &commit_fops);
+
+	return 0;
+}
+
+module_init(icc_test_init);
+module_exit(icc_test_exit);
+MODULE_LICENSE("GPL v2");
+
+#endif
--- a/include/dt-bindings/interconnect/qcom,pineapple.h
+++ b/include/dt-bindings/interconnect/qcom,pineapple.h
@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_PINEAPPLE_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_PINEAPPLE_H
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_UBWC_P_TCU				2
+#define MASTER_APPSS_PROC				3
+#define MASTER_LLCC				4
+#define MASTER_QDSS_BAM				5
+#define MASTER_QSPI_0				6
+#define MASTER_QUP_1				7
+#define MASTER_QUP_2				8
+#define MASTER_A1NOC_SNOC				9
+#define MASTER_A2NOC_SNOC				10
+#define MASTER_CAMNOC_HF				11
+#define MASTER_CAMNOC_ICP				12
+#define MASTER_CAMNOC_SF				13
+#define MASTER_GEM_NOC_CNOC				14
+#define MASTER_GEM_NOC_PCIE_SNOC				15
+#define MASTER_GFX3D				16
+#define MASTER_LPASS_GEM_NOC				17
+#define MASTER_LPASS_LPINOC				18
+#define MASTER_LPIAON_NOC				19
+#define MASTER_MDP				20
+#define MASTER_MSS_PROC				21
+#define MASTER_MNOC_HF_MEM_NOC				22
+#define MASTER_MNOC_SF_MEM_NOC				23
+#define MASTER_CDSP_PROC				24
+#define MASTER_COMPUTE_NOC				25
+#define MASTER_ANOC_PCIE_GEM_NOC				26
+#define MASTER_SNOC_SF_MEM_NOC				27
+#define MASTER_UBWC_P				28
+#define MASTER_CDSP_HCP				29
+#define MASTER_VIDEO				30
+#define MASTER_VIDEO_CV_PROC				31
+#define MASTER_VIDEO_PROC				32
+#define MASTER_VIDEO_V_PROC				33
+#define MASTER_CNOC_CFG				34
+#define MASTER_CNOC_MNOC_CFG				35
+#define MASTER_PCIE_ANOC_CFG				36
+#define MASTER_QUP_CORE_0				37
+#define MASTER_QUP_CORE_1				38
+#define MASTER_QUP_CORE_2				39
+#define MASTER_CRYPTO				40
+#define MASTER_IPA				41
+#define MASTER_LPASS_PROC				42
+#define MASTER_QUP_3				43
+#define MASTER_SP				44
+#define MASTER_GIC				45
+#define MASTER_PCIE_0				46
+#define MASTER_PCIE_1				47
+#define MASTER_QDSS_ETR				48
+#define MASTER_QDSS_ETR_1				49
+#define MASTER_SDCC_2				50
+#define MASTER_SDCC_4				51
+#define MASTER_UFS_MEM				52
+#define MASTER_USB3_0				53
+#define SLAVE_EBI1				512
+#define SLAVE_AHB2PHY_SOUTH				513
+#define SLAVE_AHB2PHY_NORTH				514
+#define SLAVE_AOSS				515
+#define SLAVE_CAMERA_CFG				516
+#define SLAVE_CLK_CTL				517
+#define SLAVE_RBCPR_CX_CFG				518
+#define SLAVE_CPR_HMX				519
+#define SLAVE_RBCPR_MMCX_CFG				520
+#define SLAVE_RBCPR_MXA_CFG				521
+#define SLAVE_RBCPR_MXC_CFG				522
+#define SLAVE_CPR_NSPCX				523
+#define SLAVE_CRYPTO_0_CFG				524
+#define SLAVE_CX_RDPM				525
+#define SLAVE_DISPLAY_CFG				526
+#define SLAVE_GFX3D_CFG				527
+#define SLAVE_I2C				528
+#define SLAVE_I3C_IBI0_CFG				529
+#define SLAVE_I3C_IBI1_CFG				530
+#define SLAVE_IMEM_CFG				531
+#define SLAVE_IPA_CFG				532
+#define SLAVE_IPC_ROUTER_CFG				533
+#define SLAVE_CNOC_MSS				534
+#define SLAVE_MX_2_RDPM				535
+#define SLAVE_MX_RDPM				536
+#define SLAVE_PCIE_0_CFG				537
+#define SLAVE_PCIE_1_CFG				538
+#define SLAVE_PCIE_RSCC				539
+#define SLAVE_PDM				540
+#define SLAVE_PRNG				541
+#define SLAVE_QDSS_CFG				542
+#define SLAVE_QSPI_0				543
+#define SLAVE_QUP_3				544
+#define SLAVE_QUP_1				545
+#define SLAVE_QUP_2				546
+#define SLAVE_SDCC_2				547
+#define SLAVE_SDCC_4				548
+#define SLAVE_SPSS_CFG				549
+#define SLAVE_TCSR				550
+#define SLAVE_TLMM				551
+#define SLAVE_TME_CFG				552
+#define SLAVE_UFS_MEM_CFG				553
+#define SLAVE_USB3_0				554
+#define SLAVE_VENUS_CFG				555
+#define SLAVE_VSENSE_CTRL_CFG				556
+#define SLAVE_A1NOC_SNOC				557
+#define SLAVE_A2NOC_SNOC				558
+#define SLAVE_GEM_NOC_CNOC				559
+#define SLAVE_SNOC_GEM_NOC_SF				560
+#define SLAVE_LLCC				561
+#define SLAVE_LPASS_GEM_NOC				562
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC				563
+#define SLAVE_LPICX_NOC_LPIAON_NOC				564
+#define SLAVE_MNOC_HF_MEM_NOC				565
+#define SLAVE_MNOC_SF_MEM_NOC				566
+#define SLAVE_CDSP_MEM_NOC				567
+#define SLAVE_MEM_NOC_PCIE_SNOC				568
+#define SLAVE_ANOC_PCIE_GEM_NOC				569
+#define SLAVE_APPSS				570
+#define SLAVE_CNOC_CFG				571
+#define SLAVE_DDRSS_CFG				572
+#define SLAVE_CNOC_MNOC_CFG				573
+#define SLAVE_NSP_QTB_CFG				574
+#define SLAVE_PCIE_ANOC_CFG				575
+#define SLAVE_QUP_CORE_0				576
+#define SLAVE_QUP_CORE_1				577
+#define SLAVE_QUP_CORE_2				578
+#define SLAVE_IMEM				579
+#define SLAVE_SERVICE_CNOC_CFG				580
+#define SLAVE_SERVICE_CNOC				581
+#define SLAVE_SERVICE_MNOC				582
+#define SLAVE_SERVICE_PCIE_ANOC				583
+#define SLAVE_PCIE_0				584
+#define SLAVE_QDSS_STM				585
+#define SLAVE_TCU				586
+#define MASTER_LLCC_DISP				1000
+#define MASTER_MDP_DISP				1001
+#define MASTER_MNOC_HF_MEM_NOC_DISP				1002
+#define MASTER_ANOC_PCIE_GEM_NOC_DISP				1003
+#define SLAVE_EBI1_DISP				1512
+#define SLAVE_LLCC_DISP				1513
+#define SLAVE_MNOC_HF_MEM_NOC_DISP				1514
+#define MASTER_LLCC_CAM_IFE_0				2000
+#define MASTER_CAMNOC_HF_CAM_IFE_0				2001
+#define MASTER_CAMNOC_ICP_CAM_IFE_0				2002
+#define MASTER_CAMNOC_SF_CAM_IFE_0				2003
+#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0				2004
+#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0				2005
+#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0				2006
+#define SLAVE_EBI1_CAM_IFE_0				2512
+#define SLAVE_LLCC_CAM_IFE_0				2513
+#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0				2514
+#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0				2515
+#define MASTER_LLCC_CAM_IFE_1				3000
+#define MASTER_CAMNOC_HF_CAM_IFE_1				3001
+#define MASTER_CAMNOC_ICP_CAM_IFE_1				3002
+#define MASTER_CAMNOC_SF_CAM_IFE_1				3003
+#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1				3004
+#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1				3005
+#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1				3006
+#define SLAVE_EBI1_CAM_IFE_1				3512
+#define SLAVE_LLCC_CAM_IFE_1				3513
+#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1				3514
+#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1				3515
+#define MASTER_LLCC_CAM_IFE_2				4000
+#define MASTER_CAMNOC_HF_CAM_IFE_2				4001
+#define MASTER_CAMNOC_ICP_CAM_IFE_2				4002
+#define MASTER_CAMNOC_SF_CAM_IFE_2				4003
+#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2				4004
+#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2				4005
+#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2				4006
+#define SLAVE_EBI1_CAM_IFE_2				4512
+#define SLAVE_LLCC_CAM_IFE_2				4513
+#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2				4514
+#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2				4515
+
+#endif