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dt-bindings: mtd: Split ECC engine with rawnand controller
Split MediaTek ECC engine with rawnand controller and convert to YAML schema. Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230201021500.26769-2-xiangsheng.hou@mediatek.com
This commit is contained in:
Xiangsheng Hou
Miquel Raynal
parent
b56265257d
commit
3af7ade257
155
Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
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155
Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
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@ -0,0 +1,155 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
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maintainers:
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- Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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properties:
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compatible:
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enum:
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- mediatek,mt2701-nfc
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- mediatek,mt2712-nfc
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- mediatek,mt7622-nfc
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reg:
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items:
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- description: Base physical address and size of NFI.
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interrupts:
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items:
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- description: NFI interrupt
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clocks:
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items:
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- description: clock used for the controller
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- description: clock used for the pad
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clock-names:
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items:
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- const: nfi_clk
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- const: pad_clk
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ecc-engine:
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description: device-tree node of the required ECC engine.
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$ref: /schemas/types.yaml#/definitions/phandle
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patternProperties:
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"^nand@[a-f0-9]$":
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$ref: nand-chip.yaml#
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unevaluatedProperties: false
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properties:
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reg:
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maximum: 1
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nand-on-flash-bbt: true
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nand-ecc-mode:
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const: hw
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allOf:
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- $ref: nand-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt2701-nfc
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then:
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patternProperties:
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"^nand@[a-f0-9]$":
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properties:
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nand-ecc-step-size:
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enum: [ 512, 1024 ]
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nand-ecc-strength:
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enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60]
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt2712-nfc
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then:
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patternProperties:
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"^nand@[a-f0-9]$":
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properties:
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nand-ecc-step-size:
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enum: [ 512, 1024 ]
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nand-ecc-strength:
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enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60, 68, 72, 80]
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt7622-nfc
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then:
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patternProperties:
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"^nand@[a-f0-9]$":
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properties:
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nand-ecc-step-size:
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const: 512
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nand-ecc-strength:
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enum: [4, 6, 8, 10, 12]
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- ecc-engine
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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nand-controller@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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nand-ecc-step-size = <1024>;
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nand-ecc-strength = <24>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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preloader@0 {
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label = "pl";
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read-only;
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reg = <0x0 0x400000>;
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};
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android@400000 {
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label = "android";
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reg = <0x400000 0x12c00000>;
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};
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};
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};
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};
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};
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@ -0,0 +1,62 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek(MTK) SoCs NAND ECC engine
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maintainers:
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- Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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description: |
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MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
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properties:
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compatible:
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enum:
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- mediatek,mt2701-ecc
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- mediatek,mt2712-ecc
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- mediatek,mt7622-ecc
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reg:
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items:
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- description: Base physical address and size of ECC.
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interrupts:
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items:
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- description: ECC interrupt
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clocks:
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maxItems: 1
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clock-names:
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const: nfiecc_clk
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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};
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};
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@ -1,176 +0,0 @@
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MTK SoCs NAND FLASH controller (NFC) DT binding
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This file documents the device tree bindings for MTK SoCs NAND controllers.
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The functional split of the controller requires two drivers to operate:
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the nand controller interface driver and the ECC engine driver.
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The hardware description for both devices must be captured as device
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tree nodes.
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1) NFC NAND Controller Interface (NFI):
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=======================================
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The first part of NFC is NAND Controller Interface (NFI) HW.
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Required NFI properties:
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- compatible: Should be one of
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"mediatek,mt2701-nfc",
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"mediatek,mt2712-nfc",
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"mediatek,mt7622-nfc".
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- reg: Base physical address and size of NFI.
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- interrupts: Interrupts of NFI.
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- clocks: NFI required clocks.
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- clock-names: NFI clocks internal name.
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- ecc-engine: Required ECC Engine node.
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- #address-cells: NAND chip index, should be 1.
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- #size-cells: Should be 0.
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Example:
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nandc: nfi@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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Platform related properties, should be set in {platform_name}.dts:
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- children nodes: NAND chips.
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Children nodes properties:
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- reg: Chip Select Signal, default 0.
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Set as reg = <0>, <1> when need 2 CS.
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Optional:
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- nand-on-flash-bbt: Store BBT on NAND Flash.
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- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
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- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
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valid values:
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512 and 1024 on mt2701 and mt2712.
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512 only on mt7622.
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1024 is recommended for large page NANDs.
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- nand-ecc-strength: Number of bits to correct per ECC step.
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The valid values that each controller supports:
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mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
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32, 36, 40, 44, 48, 52, 56, 60.
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mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
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32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
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mt7622: 4, 6, 8, 10, 12, 14, 16.
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The strength should be calculated as follows:
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E = (S - F) * 8 / B
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S = O / (P / Q)
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E : nand-ecc-strength.
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S : spare size per sector.
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F : FDM size, should be in the range [1,8].
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It is used to store free oob data.
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O : oob size.
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P : page size.
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Q : nand-ecc-step-size.
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B : number of parity bits needed to correct
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1 bitflip.
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According to MTK NAND controller design,
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this number depends on max ecc step size
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that MTK NAND controller supports.
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If max ecc step size supported is 1024,
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then it should be always 14. And if max
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ecc step size is 512, then it should be
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always 13.
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If the result does not match any one of the listed
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choices above, please select the smaller valid value from
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the list.
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(otherwise the driver will do the adjustment at runtime)
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- pinctrl-names: Default NAND pin GPIO setting name.
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- pinctrl-0: GPIO setting node.
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Example:
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&pio {
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nand_pins_default: nanddefault {
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pins_dat {
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pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
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<MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
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<MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
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<MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
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<MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
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<MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
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<MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
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<MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
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<MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
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input-enable;
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up;
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};
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pins_we {
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pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
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};
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pins_ale {
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pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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};
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};
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&nandc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins_default>;
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nand@0 {
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reg = <0>;
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <24>;
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nand-ecc-step-size = <1024>;
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};
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};
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NAND chip optional subnodes:
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- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
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Example:
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nand@0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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preloader@0 {
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label = "pl";
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read-only;
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reg = <0x00000000 0x00400000>;
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};
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android@00400000 {
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label = "android";
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reg = <0x00400000 0x12c00000>;
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};
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};
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};
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2) ECC Engine:
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==============
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Required BCH properties:
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- compatible: Should be one of
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"mediatek,mt2701-ecc",
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"mediatek,mt2712-ecc",
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"mediatek,mt7622-ecc".
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- reg: Base physical address and size of ECC.
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- interrupts: Interrupts of ECC.
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- clocks: ECC required clocks.
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- clock-names: ECC clocks internal name.
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Example:
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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};
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@ -13213,7 +13213,7 @@ F: drivers/phy/ralink/phy-mt7621-pci.c
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MEDIATEK NAND CONTROLLER DRIVER
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L: linux-mtd@lists.infradead.org
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S: Orphan
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F: Documentation/devicetree/bindings/mtd/mtk-nand.txt
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F: Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
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F: drivers/mtd/nand/raw/mtk_*
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MEDIATEK PMIC LED DRIVER
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