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drm/amdgpu: Update TCP Control register on GFX 12.1

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Update TCP CNTL register to disable some features not supported
on GFX 12.1.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2025-09-15 10:48:04 -04:00 committed by Alex Deucher
parent 258cc2b687
commit 3af6302d8c
1 changed files with 12 additions and 0 deletions
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12
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
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@ -2668,6 +2668,17 @@ static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev,
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data);
}
static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev,
int xcc_id)
{
uint32_t data;
data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL);
data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1);
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data);
}
static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev)
{
int i;
@ -2677,6 +2688,7 @@ static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev)
gfx_v12_1_xcc_enable_atomics(adev, i);
gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i);
gfx_v12_1_xcc_disable_early_write_ack(adev, i);
gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i);
}
}