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arm64: dts: exynos: axis: Add initial ARTPEC-9 SoC support
Add initial device tree support for Axis ARTPEC-9 SoC. This SoC contains 6 Cortex-A55 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://patch.msgid.link/20251119131302.79088-3-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
SungMin Park
Krzysztof Kozlowski
parent
7b43a16c48
commit
3ae2b7442c
115
arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi
Normal file
115
arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi
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@ -0,0 +1,115 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Axis ARTPEC-9 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*/
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#include "artpec-pinctrl.h"
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&pinctrl_fsys0 {
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gpe0: gpe0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe1: gpe1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe2: gpe2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe3: gpe3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe4: gpe4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf0: gpf0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf1: gpf1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpi0: gpi0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gps0: gps0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gps1: gps1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_fsys1 {
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gpu0: gpu0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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serial0_bus: serial0-bus-pins {
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samsung,pins = "gpu0-0", "gpu0-1";
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samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
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samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
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samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
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};
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};
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&pinctrl_peric {
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gpa0: gpa0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpa1: gpa1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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277
arch/arm64/boot/dts/exynos/axis/artpec9.dtsi
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277
arch/arm64/boot/dts/exynos/axis/artpec9.dtsi
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@ -0,0 +1,277 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Axis ARTPEC-9 SoC device tree source
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*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axis,artpec9-clk.h>
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/ {
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compatible = "axis,artpec9";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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pinctrl0 = &pinctrl_fsys0;
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pinctrl1 = &pinctrl_fsys1;
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pinctrl2 = &pinctrl_peric;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>;
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clock-names = "cpu";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x400>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x500>;
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enable-method = "psci";
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cpu-idle-states = <&cpu_sleep>;
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};
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idle-states {
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entry-method = "psci";
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cpu_sleep: cpu-sleep {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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};
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};
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};
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fin_pll: clock-finpll {
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compatible = "fixed-factor-clock";
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clocks = <&osc_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "fin_pll";
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};
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osc_clk: clock-osc {
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/* XXTI */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "osc_clk";
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x0 0x0 0x17000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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cmu_imem: clock-controller@10010000 {
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compatible = "axis,artpec9-cmu-imem";
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reg = <0x0 0x10010000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>,
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<&cmu_cmu CLK_DOUT_CMU_IMEM_CA5>,
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<&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>,
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<&cmu_cmu CLK_DOUT_CMU_IMEM_SSS>;
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clock-names = "fin_pll", "aclk", "ca5", "jpeg", "sss";
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};
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timer@10040000 {
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compatible = "axis,artpec9-mct", "samsung,exynos4210-mct";
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reg = <0x0 0x10040000 0x0 0x1000>;
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clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT0_PCLK>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@10400000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x10400000 0x0 0x00040000>,
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<0x0 0x10440000 0x0 0x000c0000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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redistributor-stride = <0x0 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_cpucl: clock-controller@12810000 {
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compatible = "axis,artpec9-cmu-cpucl";
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reg = <0x0 0x12810000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>;
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clock-names = "fin_pll", "switch";
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};
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cmu_cmu: clock-controller@12c00000 {
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compatible = "axis,artpec9-cmu-cmu";
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reg = <0x0 0x12c00000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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clock-names = "fin_pll";
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};
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cmu_core: clock-controller@12c10000 {
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compatible = "axis,artpec9-cmu-core";
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reg = <0x0 0x12c10000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>;
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clock-names = "fin_pll", "main";
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};
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cmu_bus: clock-controller@13410000 {
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compatible = "axis,artpec9-cmu-bus";
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reg = <0x0 0x13410000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_BUS>;
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clock-names = "fin_pll", "bus";
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};
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cmu_peri: clock-controller@14010000 {
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compatible = "axis,artpec9-cmu-peri";
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reg = <0x0 0x14010000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_PERI_IP>,
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<&cmu_cmu CLK_DOUT_CMU_PERI_DISP>;
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clock-names = "fin_pll", "ip", "disp";
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};
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pinctrl_peric: pinctrl@141f0000 {
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compatible = "axis,artpec9-pinctrl";
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reg = <0x0 0x141f0000 0x0 0x1000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_fsys0: clock-controller@14410000 {
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compatible = "axis,artpec9-cmu-fsys0";
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reg = <0x0 0x14410000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS0_BUS>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS0_IP>;
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clock-names = "fin_pll", "bus", "ip";
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};
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pinctrl_fsys0: pinctrl@14430000 {
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compatible = "axis,artpec9-pinctrl";
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reg = <0x0 0x14430000 0x0 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_fsys1: clock-controller@14c10000 {
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compatible = "axis,artpec9-cmu-fsys1";
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reg = <0x0 0x14c10000 0x0 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
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clock-names = "fin_pll", "scan0", "scan1", "bus";
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};
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pinctrl_fsys1: pinctrl@14c30000 {
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compatible = "axis,artpec9-pinctrl";
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reg = <0x0 0x14c30000 0x0 0x1000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu_system_controller: system-controller@14c40000 {
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compatible = "axis,artpec9-pmu", "samsung,exynos7-pmu", "syscon";
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reg = <0x0 0x14c40000 0x0 0x10000>;
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};
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serial_0: serial@14c70000 {
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compatible = "axis,artpec9-uart", "samsung,exynos8895-uart";
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reg = <0x0 0x14c70000 0x0 0x100>;
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clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_UART0_PCLK>,
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<&cmu_fsys1 CLK_GOUT_FSYS1_UART0_SCLK_UART>;
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clock-names = "uart", "clk_uart_baud0";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&serial0_bus>;
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samsung,uart-fifosize = <64>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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