From 3accb9534902ad30c786380f69bda159e3b9cfa4 Mon Sep 17 00:00:00 2001
From: Lin Huang <hl@rock-chips.com>
Date: Wed, 12 Sep 2018 18:00:22 +0800
Subject: [PATCH] arm64: dts: rockchip: support syr827 regulator on rk1808 evb

syr827 use for rk1808 NPU power suppply. The default voltage is 1.0v,
we need to set it to 0.85v when board boot up.

Change-Id: Id4f0c400b931d0f97801b9a70760d9ebd351ce4e
Signed-off-by: Lin Huang <hl@rock-chips.com>
---
 .../boot/dts/rockchip/rk1808-evb-v10.dts      |  9 ++++++++
 arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi  | 23 +++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts b/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts
index 1ee5fc7324d5..05b7267cedb2 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts
@@ -152,6 +152,15 @@ &vad {
 	#sound-dai-cells = <0>;
 };
 
+/*
+ * set max voltage to 850mv to fit for npu power supply request,
+ * we can change max voltage when we get more imformation.
+ */
+&vdd_npu {
+	regulator-min-microvolt = <850000>;
+	regulator-max-microvolt = <850000>;
+};
+
 &vop_lite {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
index 3b2b2e712e55..10461eebe97e 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
@@ -212,6 +212,24 @@ &emmc {
 &i2c0 {
 	status = "okay";
 
+	vdd_npu: syr837@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		pinctrl-0 = <&vsel_gpio>;
+		vsel-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_npu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
 	rk809: pmic@20 {
 		compatible = "rockchip,rk809";
 		reg = <0x20>;
@@ -585,6 +603,11 @@ soc_slppin_rst: soc_slppin_rst {
 			rockchip,pins =
 				<0 RK_PA4 2 &pcfg_pull_none>;
 		};
+
+		vsel_gpio: vsel-gpio {
+			rockchip,pins =
+				<0 RK_PA5 0 &pcfg_pull_down>;
+		};
 	};
 
 	sdio-pwrseq {