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https://github.com/torvalds/linux.git
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i.MX dt-bindings update for 6.2:
- New vendor prefix for Cloos and InnoComm. - New compatible for Cloos PHG board, InnoComm WB15 EVK and Kobo Aura 2. - Improve snvs-lpgpr bindings schema regarding i.MX8M SNVS LPGRP compatible strings. - Improve fsl-imx-cspi bindings schema for i.MX8MP ECSPI. - Add bindings schema for i.MX8M ANATOP device. - Update SCU firmware resource ID header by syncing with the latest available SCFW kit version 1.13.0. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmN4j2gUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM47OAf/Wzf7YIoFq8LNKJ/9ZCyVrcsK08dV axT7XUq5yDVbZJ2a1w0OzVJXBhF728/akN4WwmBz9UjJwsMUczNWY55GuKeEGeG5 ukWtrDPHMnrIXJsxeS/pb5a1XRIWChC8rR+3kQ7g5uaKgClZ781fFNoOrmkwdJhS 5bq4FxbAzf32RN3JTcuNHVktx5xLT2mqTea0SexaPQKbFM/nSxq1W/f/gJd7Bxix c0+ukM/wR8xz+qbZMNCjcvK+L+y159ZcURJkDHhpe+N2ljjCrQ/lUi6y8BPutK8b PLtAToVa10nWt6qaWKeHl+tLxhLjqO7OyVfz9IWHo+zE4pCBsJ/ip4TMrA== =uBMG -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmN7hBMACgkQmmx57+YA GNlPoA/+PMYAn4bvqcglA+I2llAHD2fTpxTJkeMRfxy8Tw3V7I3FCxrsQqcamLEZ IR3B+4jQrv/Mc4ZoO0015DaE7aA9BVWq0bhP8u+0FY7iKHyPyAtzo1VwrnBhwmiC MLLjxpgUbBFpJ4+sRB7VIbNYh/PqFzEPpUssRfOLIgQhCcW2c+71nIEW4fwZ42eM bwz2YinTnMwrP7xrrRvfhIvfUxPTQdB59/nE0QGp76f8r+LfpN6pA1a18mdUJVmg GwkretJ8F2atavoLxah3AWvEc1d1lhID3XcyzK2cRl8ovedqngPF2oyIxZWlYk0o e1ph3WwCFQhlMKnmrIN0H2ksuAoy/0TTHRIAHYP9PxQoKScazklILb3/7YQfh30R lQg3EouPxtEpgd3Mkl6tFpCfxzESS6J9ue6OOZyC+7ZCT7463pJ7pZgMKHx45tcy +roJHb3ztOTNMBL/yDPka6FR4P+scq1GgUI2s+idSrdnA4SQpr0j4k/1vvmII3TS aS/ZWK6bp8976RCuqET1GblqdSJIDZIQNeX4jxX70fE7egPxY9MIokjrFhNXxocv i52w5WBd7QBVXvRyHSq4mEyd2zmsn35exFntCmTeVttDZi3eiGPaaD80tCu4hUda ysYOid9nu32Gcn3T0vLXs2FnbfMQS2a8XMrbAfL1/nUmVL486zE= =1nTJ -----END PGP SIGNATURE----- Merge tag 'imx-bindings-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt i.MX dt-bindings update for 6.2: - New vendor prefix for Cloos and InnoComm. - New compatible for Cloos PHG board, InnoComm WB15 EVK and Kobo Aura 2. - Improve snvs-lpgpr bindings schema regarding i.MX8M SNVS LPGRP compatible strings. - Improve fsl-imx-cspi bindings schema for i.MX8MP ECSPI. - Add bindings schema for i.MX8M ANATOP device. - Update SCU firmware resource ID header by syncing with the latest available SCFW kit version 1.13.0. * tag 'imx-bindings-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: fsl: Add an entry for Cloos PHG board dt-bindings: vendor-prefixes: Add an entry for Cloos dt-bindings: nvmem: snvs-lpgpr: Fix i.MX8M compatible strings dt-bindings: spi: fsl-imx-cspi: update i.MX8MP binding dt-bindings: arm: fsl: add compatible string for Kobo Aura 2 dt-bindings: clock: add i.MX8M Anatop dt-bindings: arm: fsl: Add InnoComm WB15 EVK dt-bindings: vendor-prefixes: Add prefix for InnoComm dt-bindings: firmware: imx: sync with SCFW kit v1.13.0 Link: https://lore.kernel.org/r/20221119125733.32719-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
3a8a1ab8f4
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@ -520,6 +520,7 @@ properties:
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items:
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- enum:
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- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
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- kobo,aura2
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- kobo,tolino-shine2hd
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- kobo,tolino-shine3
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- kobo,tolino-vision5
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@ -814,6 +815,7 @@ properties:
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- enum:
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- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
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- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
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- cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
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- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
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- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
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- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
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@ -825,6 +827,7 @@ properties:
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- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
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- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
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- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
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- innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM
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- kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM
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- kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM
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- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
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@ -0,0 +1,51 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8m-anatop.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Family Anatop Module
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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description: |
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NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx8mm-anatop
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- fsl,imx8mq-anatop
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- items:
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- enum:
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- fsl,imx8mn-anatop
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- fsl,imx8mp-anatop
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- const: fsl,imx8mm-anatop
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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anatop: clock-controller@30360000 {
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compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
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reg = <0x30360000 0x10000>;
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#clock-cells = <1>;
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};
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...
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@ -11,14 +11,18 @@ maintainers:
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properties:
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compatible:
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enum:
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- fsl,imx6q-snvs-lpgpr
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- fsl,imx6ul-snvs-lpgpr
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- fsl,imx7d-snvs-lpgpr
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- fsl,imx8mm-snvs-lpgpr
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- fsl,imx8mn-snvs-lpgpr
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- fsl,imx8mp-snvs-lpgpr
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- fsl,imx8mq-snvs-lpgpr
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oneOf:
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- items:
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- enum:
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- fsl,imx8mm-snvs-lpgpr
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- fsl,imx8mn-snvs-lpgpr
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- fsl,imx8mp-snvs-lpgpr
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- fsl,imx8mq-snvs-lpgpr
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- const: fsl,imx7d-snvs-lpgpr
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- enum:
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- fsl,imx6q-snvs-lpgpr
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- fsl,imx6ul-snvs-lpgpr
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- fsl,imx7d-snvs-lpgpr
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required:
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- compatible
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@ -22,6 +22,9 @@ properties:
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- const: fsl,imx35-cspi
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- const: fsl,imx51-ecspi
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- const: fsl,imx53-ecspi
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- items:
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- const: fsl,imx8mp-ecspi
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- const: fsl,imx6ul-ecspi
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- items:
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- enum:
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- fsl,imx50-ecspi
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@ -34,7 +37,6 @@ properties:
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- fsl,imx8mq-ecspi
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- fsl,imx8mm-ecspi
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- fsl,imx8mn-ecspi
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- fsl,imx8mp-ecspi
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- const: fsl,imx51-ecspi
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reg:
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@ -260,6 +260,8 @@ patternProperties:
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description: Cirrus Logic, Inc.
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"^cisco,.*":
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description: Cisco Systems, Inc.
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"^cloos,.*":
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description: Carl Cloos Schweisstechnik GmbH.
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"^cloudengines,.*":
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description: Cloud Engines, Inc.
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"^cnm,.*":
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@ -605,6 +607,8 @@ patternProperties:
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description: Ingenic Semiconductor
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"^injoinic,.*":
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description: Injoinic Technology Corp.
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"^innocomm,.*":
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description: InnoComm Mobile Technology Corp.
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"^innolux,.*":
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description: Innolux Corporation
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"^inside-secure,.*":
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@ -13,30 +13,30 @@
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* never be changed or removed (only added to at the end of the list).
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*/
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#define IMX_SC_R_A53 0
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#define IMX_SC_R_A53_0 1
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#define IMX_SC_R_A53_1 2
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#define IMX_SC_R_A53_2 3
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#define IMX_SC_R_A53_3 4
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#define IMX_SC_R_A72 5
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#define IMX_SC_R_A72_0 6
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#define IMX_SC_R_A72_1 7
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#define IMX_SC_R_A72_2 8
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#define IMX_SC_R_A72_3 9
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#define IMX_SC_R_AP_0 0
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#define IMX_SC_R_AP_0_0 1
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#define IMX_SC_R_AP_0_1 2
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#define IMX_SC_R_AP_0_2 3
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#define IMX_SC_R_AP_0_3 4
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#define IMX_SC_R_AP_1 5
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#define IMX_SC_R_AP_1_0 6
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#define IMX_SC_R_AP_1_1 7
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#define IMX_SC_R_AP_1_2 8
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#define IMX_SC_R_AP_1_3 9
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#define IMX_SC_R_CCI 10
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#define IMX_SC_R_DB 11
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#define IMX_SC_R_DRC_0 12
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#define IMX_SC_R_DRC_1 13
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#define IMX_SC_R_GIC_SMMU 14
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#define IMX_SC_R_IRQSTR_M4_0 15
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#define IMX_SC_R_IRQSTR_M4_1 16
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#define IMX_SC_R_SMMU 17
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#define IMX_SC_R_GIC 18
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#define IMX_SC_R_IRQSTR_MCU_0 15
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#define IMX_SC_R_IRQSTR_MCU_1 16
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#define IMX_SC_R_SMMU_0 17
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#define IMX_SC_R_GIC_0 18
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#define IMX_SC_R_DC_0_BLIT0 19
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#define IMX_SC_R_DC_0_BLIT1 20
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#define IMX_SC_R_DC_0_BLIT2 21
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#define IMX_SC_R_DC_0_BLIT_OUT 22
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#define IMX_SC_R_PERF 23
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#define IMX_SC_R_PERF_0 23
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#define IMX_SC_R_USB_1_PHY 24
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#define IMX_SC_R_DC_0_WARP 25
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#define IMX_SC_R_V2X_MU_0 26
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@ -56,11 +56,14 @@
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#define IMX_SC_R_V2X_MU_3 40
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#define IMX_SC_R_V2X_MU_4 41
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#define IMX_SC_R_DC_1_WARP 42
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#define IMX_SC_R_STM 43
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#define IMX_SC_R_SECVIO 44
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#define IMX_SC_R_DC_1_VIDEO0 45
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#define IMX_SC_R_DC_1_VIDEO1 46
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#define IMX_SC_R_DC_1_FRAC0 47
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#define IMX_SC_R_V2X 48
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#define IMX_SC_R_DC_1 49
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#define IMX_SC_R_UNUSED14 50
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#define IMX_SC_R_DC_1_PLL_0 51
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#define IMX_SC_R_DC_1_PLL_1 52
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#define IMX_SC_R_SPI_0 53
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@ -151,10 +154,10 @@
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#define IMX_SC_R_DMA_1_CH29 137
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#define IMX_SC_R_DMA_1_CH30 138
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#define IMX_SC_R_DMA_1_CH31 139
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#define IMX_SC_R_UNUSED1 140
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#define IMX_SC_R_UNUSED2 141
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#define IMX_SC_R_UNUSED3 142
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#define IMX_SC_R_UNUSED4 143
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#define IMX_SC_R_V2X_PID0 140
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#define IMX_SC_R_V2X_PID1 141
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#define IMX_SC_R_V2X_PID2 142
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#define IMX_SC_R_V2X_PID3 143
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#define IMX_SC_R_GPU_0_PID0 144
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#define IMX_SC_R_GPU_0_PID1 145
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#define IMX_SC_R_GPU_0_PID2 146
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@ -183,7 +186,7 @@
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#define IMX_SC_R_PCIE_B 169
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#define IMX_SC_R_SATA_0 170
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#define IMX_SC_R_SERDES_1 171
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#define IMX_SC_R_HSIO_GPIO 172
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#define IMX_SC_R_HSIO_GPIO_0 172
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#define IMX_SC_R_MATCH_15 173
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#define IMX_SC_R_MATCH_16 174
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#define IMX_SC_R_MATCH_17 175
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@ -250,15 +253,15 @@
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#define IMX_SC_R_ROM_0 236
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#define IMX_SC_R_FSPI_0 237
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#define IMX_SC_R_FSPI_1 238
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#define IMX_SC_R_IEE 239
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#define IMX_SC_R_IEE_R0 240
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#define IMX_SC_R_IEE_R1 241
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#define IMX_SC_R_IEE_R2 242
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#define IMX_SC_R_IEE_R3 243
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#define IMX_SC_R_IEE_R4 244
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#define IMX_SC_R_IEE_R5 245
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#define IMX_SC_R_IEE_R6 246
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#define IMX_SC_R_IEE_R7 247
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#define IMX_SC_R_IEE_0 239
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||||
#define IMX_SC_R_IEE_0_R0 240
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#define IMX_SC_R_IEE_0_R1 241
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||||
#define IMX_SC_R_IEE_0_R2 242
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||||
#define IMX_SC_R_IEE_0_R3 243
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||||
#define IMX_SC_R_IEE_0_R4 244
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#define IMX_SC_R_IEE_0_R5 245
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#define IMX_SC_R_IEE_0_R6 246
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#define IMX_SC_R_IEE_0_R7 247
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#define IMX_SC_R_SDHC_0 248
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#define IMX_SC_R_SDHC_1 249
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||||
#define IMX_SC_R_SDHC_2 250
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|
|
@ -289,46 +292,50 @@
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|||
#define IMX_SC_R_LVDS_2_PWM_0 275
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#define IMX_SC_R_LVDS_2_I2C_0 276
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#define IMX_SC_R_LVDS_2_I2C_1 277
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#define IMX_SC_R_M4_0_PID0 278
|
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#define IMX_SC_R_M4_0_PID1 279
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#define IMX_SC_R_M4_0_PID2 280
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#define IMX_SC_R_M4_0_PID3 281
|
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#define IMX_SC_R_M4_0_PID4 282
|
||||
#define IMX_SC_R_M4_0_RGPIO 283
|
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#define IMX_SC_R_M4_0_SEMA42 284
|
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#define IMX_SC_R_M4_0_TPM 285
|
||||
#define IMX_SC_R_M4_0_PIT 286
|
||||
#define IMX_SC_R_M4_0_UART 287
|
||||
#define IMX_SC_R_M4_0_I2C 288
|
||||
#define IMX_SC_R_M4_0_INTMUX 289
|
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#define IMX_SC_R_M4_0_MU_0B 292
|
||||
#define IMX_SC_R_M4_0_MU_0A0 293
|
||||
#define IMX_SC_R_M4_0_MU_0A1 294
|
||||
#define IMX_SC_R_M4_0_MU_0A2 295
|
||||
#define IMX_SC_R_M4_0_MU_0A3 296
|
||||
#define IMX_SC_R_M4_0_MU_1A 297
|
||||
#define IMX_SC_R_M4_1_PID0 298
|
||||
#define IMX_SC_R_M4_1_PID1 299
|
||||
#define IMX_SC_R_M4_1_PID2 300
|
||||
#define IMX_SC_R_M4_1_PID3 301
|
||||
#define IMX_SC_R_M4_1_PID4 302
|
||||
#define IMX_SC_R_M4_1_RGPIO 303
|
||||
#define IMX_SC_R_M4_1_SEMA42 304
|
||||
#define IMX_SC_R_M4_1_TPM 305
|
||||
#define IMX_SC_R_M4_1_PIT 306
|
||||
#define IMX_SC_R_M4_1_UART 307
|
||||
#define IMX_SC_R_M4_1_I2C 308
|
||||
#define IMX_SC_R_M4_1_INTMUX 309
|
||||
#define IMX_SC_R_M4_1_MU_0B 312
|
||||
#define IMX_SC_R_M4_1_MU_0A0 313
|
||||
#define IMX_SC_R_M4_1_MU_0A1 314
|
||||
#define IMX_SC_R_M4_1_MU_0A2 315
|
||||
#define IMX_SC_R_M4_1_MU_0A3 316
|
||||
#define IMX_SC_R_M4_1_MU_1A 317
|
||||
#define IMX_SC_R_MCU_0_PID0 278
|
||||
#define IMX_SC_R_MCU_0_PID1 279
|
||||
#define IMX_SC_R_MCU_0_PID2 280
|
||||
#define IMX_SC_R_MCU_0_PID3 281
|
||||
#define IMX_SC_R_MCU_0_PID4 282
|
||||
#define IMX_SC_R_MCU_0_RGPIO 283
|
||||
#define IMX_SC_R_MCU_0_SEMA42 284
|
||||
#define IMX_SC_R_MCU_0_TPM 285
|
||||
#define IMX_SC_R_MCU_0_PIT 286
|
||||
#define IMX_SC_R_MCU_0_UART 287
|
||||
#define IMX_SC_R_MCU_0_I2C 288
|
||||
#define IMX_SC_R_MCU_0_INTMUX 289
|
||||
#define IMX_SC_R_ENET_0_A0 290
|
||||
#define IMX_SC_R_ENET_0_A1 291
|
||||
#define IMX_SC_R_MCU_0_MU_0B 292
|
||||
#define IMX_SC_R_MCU_0_MU_0A0 293
|
||||
#define IMX_SC_R_MCU_0_MU_0A1 294
|
||||
#define IMX_SC_R_MCU_0_MU_0A2 295
|
||||
#define IMX_SC_R_MCU_0_MU_0A3 296
|
||||
#define IMX_SC_R_MCU_0_MU_1A 297
|
||||
#define IMX_SC_R_MCU_1_PID0 298
|
||||
#define IMX_SC_R_MCU_1_PID1 299
|
||||
#define IMX_SC_R_MCU_1_PID2 300
|
||||
#define IMX_SC_R_MCU_1_PID3 301
|
||||
#define IMX_SC_R_MCU_1_PID4 302
|
||||
#define IMX_SC_R_MCU_1_RGPIO 303
|
||||
#define IMX_SC_R_MCU_1_SEMA42 304
|
||||
#define IMX_SC_R_MCU_1_TPM 305
|
||||
#define IMX_SC_R_MCU_1_PIT 306
|
||||
#define IMX_SC_R_MCU_1_UART 307
|
||||
#define IMX_SC_R_MCU_1_I2C 308
|
||||
#define IMX_SC_R_MCU_1_INTMUX 309
|
||||
#define IMX_SC_R_UNUSED17 310
|
||||
#define IMX_SC_R_UNUSED18 311
|
||||
#define IMX_SC_R_MCU_1_MU_0B 312
|
||||
#define IMX_SC_R_MCU_1_MU_0A0 313
|
||||
#define IMX_SC_R_MCU_1_MU_0A1 314
|
||||
#define IMX_SC_R_MCU_1_MU_0A2 315
|
||||
#define IMX_SC_R_MCU_1_MU_0A3 316
|
||||
#define IMX_SC_R_MCU_1_MU_1A 317
|
||||
#define IMX_SC_R_SAI_0 318
|
||||
#define IMX_SC_R_SAI_1 319
|
||||
#define IMX_SC_R_SAI_2 320
|
||||
#define IMX_SC_R_IRQSTR_SCU2 321
|
||||
#define IMX_SC_R_IRQSTR_AP_0 321
|
||||
#define IMX_SC_R_IRQSTR_DSP 322
|
||||
#define IMX_SC_R_ELCDIF_PLL 323
|
||||
#define IMX_SC_R_OCRAM 324
|
||||
|
|
@ -373,33 +380,33 @@
|
|||
#define IMX_SC_R_VPU_PID5 363
|
||||
#define IMX_SC_R_VPU_PID6 364
|
||||
#define IMX_SC_R_VPU_PID7 365
|
||||
#define IMX_SC_R_VPU_UART 366
|
||||
#define IMX_SC_R_VPUCORE 367
|
||||
#define IMX_SC_R_VPUCORE_0 368
|
||||
#define IMX_SC_R_VPUCORE_1 369
|
||||
#define IMX_SC_R_VPUCORE_2 370
|
||||
#define IMX_SC_R_VPUCORE_3 371
|
||||
#define IMX_SC_R_ENET_0_A2 366
|
||||
#define IMX_SC_R_ENET_1_A0 367
|
||||
#define IMX_SC_R_ENET_1_A1 368
|
||||
#define IMX_SC_R_ENET_1_A2 369
|
||||
#define IMX_SC_R_ENET_1_A3 370
|
||||
#define IMX_SC_R_ENET_1_A4 371
|
||||
#define IMX_SC_R_DMA_4_CH0 372
|
||||
#define IMX_SC_R_DMA_4_CH1 373
|
||||
#define IMX_SC_R_DMA_4_CH2 374
|
||||
#define IMX_SC_R_DMA_4_CH3 375
|
||||
#define IMX_SC_R_DMA_4_CH4 376
|
||||
#define IMX_SC_R_ISI_CH0 377
|
||||
#define IMX_SC_R_ISI_CH1 378
|
||||
#define IMX_SC_R_ISI_CH2 379
|
||||
#define IMX_SC_R_ISI_CH3 380
|
||||
#define IMX_SC_R_ISI_CH4 381
|
||||
#define IMX_SC_R_ISI_CH5 382
|
||||
#define IMX_SC_R_ISI_CH6 383
|
||||
#define IMX_SC_R_ISI_CH7 384
|
||||
#define IMX_SC_R_MJPEG_DEC_S0 385
|
||||
#define IMX_SC_R_MJPEG_DEC_S1 386
|
||||
#define IMX_SC_R_MJPEG_DEC_S2 387
|
||||
#define IMX_SC_R_MJPEG_DEC_S3 388
|
||||
#define IMX_SC_R_MJPEG_ENC_S0 389
|
||||
#define IMX_SC_R_MJPEG_ENC_S1 390
|
||||
#define IMX_SC_R_MJPEG_ENC_S2 391
|
||||
#define IMX_SC_R_MJPEG_ENC_S3 392
|
||||
#define IMX_SC_R_ISI_0_CH0 377
|
||||
#define IMX_SC_R_ISI_0_CH1 378
|
||||
#define IMX_SC_R_ISI_0_CH2 379
|
||||
#define IMX_SC_R_ISI_0_CH3 380
|
||||
#define IMX_SC_R_ISI_0_CH4 381
|
||||
#define IMX_SC_R_ISI_0_CH5 382
|
||||
#define IMX_SC_R_ISI_0_CH6 383
|
||||
#define IMX_SC_R_ISI_0_CH7 384
|
||||
#define IMX_SC_R_MJPEG_0_DEC_S0 385
|
||||
#define IMX_SC_R_MJPEG_0_DEC_S1 386
|
||||
#define IMX_SC_R_MJPEG_0_DEC_S2 387
|
||||
#define IMX_SC_R_MJPEG_0_DEC_S3 388
|
||||
#define IMX_SC_R_MJPEG_0_ENC_S0 389
|
||||
#define IMX_SC_R_MJPEG_0_ENC_S1 390
|
||||
#define IMX_SC_R_MJPEG_0_ENC_S2 391
|
||||
#define IMX_SC_R_MJPEG_0_ENC_S3 392
|
||||
#define IMX_SC_R_MIPI_0 393
|
||||
#define IMX_SC_R_MIPI_0_PWM_0 394
|
||||
#define IMX_SC_R_MIPI_0_I2C_0 395
|
||||
|
|
@ -514,11 +521,11 @@
|
|||
#define IMX_SC_R_SECO_MU_3 504
|
||||
#define IMX_SC_R_SECO_MU_4 505
|
||||
#define IMX_SC_R_HDMI_RX_PWM_0 506
|
||||
#define IMX_SC_R_A35 507
|
||||
#define IMX_SC_R_A35_0 508
|
||||
#define IMX_SC_R_A35_1 509
|
||||
#define IMX_SC_R_A35_2 510
|
||||
#define IMX_SC_R_A35_3 511
|
||||
#define IMX_SC_R_AP_2 507
|
||||
#define IMX_SC_R_AP_2_0 508
|
||||
#define IMX_SC_R_AP_2_1 509
|
||||
#define IMX_SC_R_AP_2_2 510
|
||||
#define IMX_SC_R_AP_2_3 511
|
||||
#define IMX_SC_R_DSP 512
|
||||
#define IMX_SC_R_DSP_RAM 513
|
||||
#define IMX_SC_R_CAAM_JR1_OUT 514
|
||||
|
|
@ -539,8 +546,8 @@
|
|||
#define IMX_SC_R_BOARD_R5 529
|
||||
#define IMX_SC_R_BOARD_R6 530
|
||||
#define IMX_SC_R_BOARD_R7 531
|
||||
#define IMX_SC_R_MJPEG_DEC_MP 532
|
||||
#define IMX_SC_R_MJPEG_ENC_MP 533
|
||||
#define IMX_SC_R_MJPEG_0_DEC_MP 532
|
||||
#define IMX_SC_R_MJPEG_0_ENC_MP 533
|
||||
#define IMX_SC_R_VPU_TS_0 534
|
||||
#define IMX_SC_R_VPU_MU_0 535
|
||||
#define IMX_SC_R_VPU_MU_1 536
|
||||
|
|
@ -572,6 +579,105 @@
|
|||
#define IMX_SC_PM_CLK_PLL 4 /* PLL */
|
||||
#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
|
||||
|
||||
/*
|
||||
* Compatibility defines for sc_rsrc_t
|
||||
*/
|
||||
#define IMX_SC_R_A35 IMX_SC_R_AP_2
|
||||
#define IMX_SC_R_A35_0 IMX_SC_R_AP_2_0
|
||||
#define IMX_SC_R_A35_1 IMX_SC_R_AP_2_1
|
||||
#define IMX_SC_R_A35_2 IMX_SC_R_AP_2_2
|
||||
#define IMX_SC_R_A35_3 IMX_SC_R_AP_2_3
|
||||
#define IMX_SC_R_A53 IMX_SC_R_AP_0
|
||||
#define IMX_SC_R_A53_0 IMX_SC_R_AP_0_0
|
||||
#define IMX_SC_R_A53_1 IMX_SC_R_AP_0_1
|
||||
#define IMX_SC_R_A53_2 IMX_SC_R_AP_0_2
|
||||
#define IMX_SC_R_A53_3 IMX_SC_R_AP_0_3
|
||||
#define IMX_SC_R_A72 IMX_SC_R_AP_1
|
||||
#define IMX_SC_R_A72_0 IMX_SC_R_AP_1_0
|
||||
#define IMX_SC_R_A72_1 IMX_SC_R_AP_1_1
|
||||
#define IMX_SC_R_A72_2 IMX_SC_R_AP_1_2
|
||||
#define IMX_SC_R_A72_3 IMX_SC_R_AP_1_3
|
||||
#define IMX_SC_R_GIC IMX_SC_R_GIC_0
|
||||
#define IMX_SC_R_HSIO_GPIO IMX_SC_R_HSIO_GPIO_0
|
||||
#define IMX_SC_R_IEE IMX_SC_R_IEE_0
|
||||
#define IMX_SC_R_IEE_R0 IMX_SC_R_IEE_0_R0
|
||||
#define IMX_SC_R_IEE_R1 IMX_SC_R_IEE_0_R1
|
||||
#define IMX_SC_R_IEE_R2 IMX_SC_R_IEE_0_R2
|
||||
#define IMX_SC_R_IEE_R3 IMX_SC_R_IEE_0_R3
|
||||
#define IMX_SC_R_IEE_R4 IMX_SC_R_IEE_0_R4
|
||||
#define IMX_SC_R_IEE_R5 IMX_SC_R_IEE_0_R5
|
||||
#define IMX_SC_R_IEE_R6 IMX_SC_R_IEE_0_R6
|
||||
#define IMX_SC_R_IEE_R7 IMX_SC_R_IEE_0_R7
|
||||
#define IMX_SC_R_IRQSTR_M4_0 IMX_SC_R_IRQSTR_MCU_0
|
||||
#define IMX_SC_R_IRQSTR_M4_1 IMX_SC_R_IRQSTR_MCU_1
|
||||
#define IMX_SC_R_IRQSTR_SCU2 IMX_SC_R_IRQSTR_AP_0
|
||||
#define IMX_SC_R_ISI_CH0 IMX_SC_R_ISI_0_CH0
|
||||
#define IMX_SC_R_ISI_CH1 IMX_SC_R_ISI_0_CH1
|
||||
#define IMX_SC_R_ISI_CH2 IMX_SC_R_ISI_0_CH2
|
||||
#define IMX_SC_R_ISI_CH3 IMX_SC_R_ISI_0_CH3
|
||||
#define IMX_SC_R_ISI_CH4 IMX_SC_R_ISI_0_CH4
|
||||
#define IMX_SC_R_ISI_CH5 IMX_SC_R_ISI_0_CH5
|
||||
#define IMX_SC_R_ISI_CH6 IMX_SC_R_ISI_0_CH6
|
||||
#define IMX_SC_R_ISI_CH7 IMX_SC_R_ISI_0_CH7
|
||||
#define IMX_SC_R_M4_0_I2C IMX_SC_R_MCU_0_I2C
|
||||
#define IMX_SC_R_M4_0_INTMUX IMX_SC_R_MCU_0_INTMUX
|
||||
#define IMX_SC_R_M4_0_MU_0A0 IMX_SC_R_MCU_0_MU_0A0
|
||||
#define IMX_SC_R_M4_0_MU_0A1 IMX_SC_R_MCU_0_MU_0A1
|
||||
#define IMX_SC_R_M4_0_MU_0A2 IMX_SC_R_MCU_0_MU_0A2
|
||||
#define IMX_SC_R_M4_0_MU_0A3 IMX_SC_R_MCU_0_MU_0A3
|
||||
#define IMX_SC_R_M4_0_MU_0B IMX_SC_R_MCU_0_MU_0B
|
||||
#define IMX_SC_R_M4_0_MU_1A IMX_SC_R_MCU_0_MU_1A
|
||||
#define IMX_SC_R_M4_0_PID0 IMX_SC_R_MCU_0_PID0
|
||||
#define IMX_SC_R_M4_0_PID1 IMX_SC_R_MCU_0_PID1
|
||||
#define IMX_SC_R_M4_0_PID2 IMX_SC_R_MCU_0_PID2
|
||||
#define IMX_SC_R_M4_0_PID3 IMX_SC_R_MCU_0_PID3
|
||||
#define IMX_SC_R_M4_0_PID4 IMX_SC_R_MCU_0_PID4
|
||||
#define IMX_SC_R_M4_0_PIT IMX_SC_R_MCU_0_PIT
|
||||
#define IMX_SC_R_M4_0_RGPIO IMX_SC_R_MCU_0_RGPIO
|
||||
#define IMX_SC_R_M4_0_SEMA42 IMX_SC_R_MCU_0_SEMA42
|
||||
#define IMX_SC_R_M4_0_TPM IMX_SC_R_MCU_0_TPM
|
||||
#define IMX_SC_R_M4_0_UART IMX_SC_R_MCU_0_UART
|
||||
#define IMX_SC_R_M4_1_I2C IMX_SC_R_MCU_1_I2C
|
||||
#define IMX_SC_R_M4_1_INTMUX IMX_SC_R_MCU_1_INTMUX
|
||||
#define IMX_SC_R_M4_1_MU_0A0 IMX_SC_R_MCU_1_MU_0A0
|
||||
#define IMX_SC_R_M4_1_MU_0A1 IMX_SC_R_MCU_1_MU_0A1
|
||||
#define IMX_SC_R_M4_1_MU_0A2 IMX_SC_R_MCU_1_MU_0A2
|
||||
#define IMX_SC_R_M4_1_MU_0A3 IMX_SC_R_MCU_1_MU_0A3
|
||||
#define IMX_SC_R_M4_1_MU_0B IMX_SC_R_MCU_1_MU_0B
|
||||
#define IMX_SC_R_M4_1_MU_1A IMX_SC_R_MCU_1_MU_1A
|
||||
#define IMX_SC_R_M4_1_PID0 IMX_SC_R_MCU_1_PID0
|
||||
#define IMX_SC_R_M4_1_PID1 IMX_SC_R_MCU_1_PID1
|
||||
#define IMX_SC_R_M4_1_PID2 IMX_SC_R_MCU_1_PID2
|
||||
#define IMX_SC_R_M4_1_PID3 IMX_SC_R_MCU_1_PID3
|
||||
#define IMX_SC_R_M4_1_PID4 IMX_SC_R_MCU_1_PID4
|
||||
#define IMX_SC_R_M4_1_PIT IMX_SC_R_MCU_1_PIT
|
||||
#define IMX_SC_R_M4_1_RGPIO IMX_SC_R_MCU_1_RGPIO
|
||||
#define IMX_SC_R_M4_1_SEMA42 IMX_SC_R_MCU_1_SEMA42
|
||||
#define IMX_SC_R_M4_1_TPM IMX_SC_R_MCU_1_TPM
|
||||
#define IMX_SC_R_M4_1_UART IMX_SC_R_MCU_1_UART
|
||||
#define IMX_SC_R_MJPEG_DEC_MP IMX_SC_R_MJPEG_0_DEC_MP
|
||||
#define IMX_SC_R_MJPEG_DEC_S0 IMX_SC_R_MJPEG_0_DEC_S0
|
||||
#define IMX_SC_R_MJPEG_DEC_S1 IMX_SC_R_MJPEG_0_DEC_S1
|
||||
#define IMX_SC_R_MJPEG_DEC_S2 IMX_SC_R_MJPEG_0_DEC_S2
|
||||
#define IMX_SC_R_MJPEG_DEC_S3 IMX_SC_R_MJPEG_0_DEC_S3
|
||||
#define IMX_SC_R_MJPEG_ENC_MP IMX_SC_R_MJPEG_0_ENC_MP
|
||||
#define IMX_SC_R_MJPEG_ENC_S0 IMX_SC_R_MJPEG_0_ENC_S0
|
||||
#define IMX_SC_R_MJPEG_ENC_S1 IMX_SC_R_MJPEG_0_ENC_S1
|
||||
#define IMX_SC_R_MJPEG_ENC_S2 IMX_SC_R_MJPEG_0_ENC_S2
|
||||
#define IMX_SC_R_MJPEG_ENC_S3 IMX_SC_R_MJPEG_0_ENC_S3
|
||||
#define IMX_SC_R_PERF IMX_SC_R_PERF_0
|
||||
#define IMX_SC_R_SMMU IMX_SC_R_SMMU_0
|
||||
#define IMX_SC_R_VPU_UART IMX_SC_R_ENET_0_A2
|
||||
#define IMX_SC_R_VPUCORE IMX_SC_R_ENET_1_A0
|
||||
#define IMX_SC_R_VPUCORE_0 IMX_SC_R_ENET_1_A1
|
||||
#define IMX_SC_R_VPUCORE_1 IMX_SC_R_ENET_1_A2
|
||||
#define IMX_SC_R_VPUCORE_2 IMX_SC_R_ENET_1_A3
|
||||
#define IMX_SC_R_VPUCORE_3 IMX_SC_R_ENET_1_A4
|
||||
#define IMX_SC_R_UNUSED1 IMX_SC_R_V2X_PID0
|
||||
#define IMX_SC_R_UNUSED2 IMX_SC_R_V2X_PID1
|
||||
#define IMX_SC_R_UNUSED3 IMX_SC_R_V2X_PID2
|
||||
#define IMX_SC_R_UNUSED4 IMX_SC_R_V2X_PID3
|
||||
|
||||
/*
|
||||
* Defines for SC CONTROL
|
||||
*/
|
||||
|
|
@ -637,6 +743,10 @@
|
|||
#define IMX_SC_C_INTF_SEL 59
|
||||
#define IMX_SC_C_RXC_DLY 60
|
||||
#define IMX_SC_C_TIMER_SEL 61
|
||||
#define IMX_SC_C_LAST 62
|
||||
#define IMX_SC_C_MISC0 62
|
||||
#define IMX_SC_C_MISC1 63
|
||||
#define IMX_SC_C_MISC2 64
|
||||
#define IMX_SC_C_MISC3 65
|
||||
#define IMX_SC_C_LAST 66
|
||||
|
||||
#endif /* __DT_BINDINGS_RSCRC_IMX_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user