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Merge branch 'icc-retire-macros' into icc-next

Browse Source 
This is ripped out of the bigger patch series at [1], as this part
doesn't really have any dependencies and (hopefully) brings no
functional change.

Compile-tested for the most part, bloat-o-meter reports no size change

[1] https://lore.kernel.org/linux-arm-msm/20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org/

* icc-retire-macros
  interconnect: qcom: sc7180: Retire DEFINE_QNODE
  interconnect: qcom: sdm670: Retire DEFINE_QNODE
  interconnect: qcom: sdm845: Retire DEFINE_QNODE
  interconnect: qcom: sdx55: Retire DEFINE_QNODE
  interconnect: qcom: sdx65: Retire DEFINE_QNODE
  interconnect: qcom: sm6350: Retire DEFINE_QNODE
  interconnect: qcom: sm8150: Retire DEFINE_QNODE
  interconnect: qcom: sm8250: Retire DEFINE_QNODE
  interconnect: qcom: sm8350: Retire DEFINE_QNODE
  interconnect: qcom: icc-rpmh: Retire DEFINE_QNODE
  interconnect: qcom: sc7180: Retire DEFINE_QBCM
  interconnect: qcom: sdm670: Retire DEFINE_QBCM
  interconnect: qcom: sdm845: Retire DEFINE_QBCM
  interconnect: qcom: sdx55: Retire DEFINE_QBCM
  interconnect: qcom: sdx65: Retire DEFINE_QBCM
  interconnect: qcom: sm6350: Retire DEFINE_QBCM
  interconnect: qcom: sm8150: Retire DEFINE_QBCM
  interconnect: qcom: sm8250: Retire DEFINE_QBCM
  interconnect: qcom: sm8350: Retire DEFINE_QBCM
  interconnect: qcom: icc-rpmh: Retire DEFINE_QBCM

Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-0-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2023-08-22 15:08:23 +03:00
commit 3a60e2a1c8
11 changed files with 11778 additions and 1306 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/interconnect/qcom/bcm-voter.h
View File

@ -12,14 +12,6 @@
#include "icc-rpmh.h"
#define DEFINE_QBCM(_name, _bcmname, _keepalive, ...) \
static struct qcom_icc_bcm _name = { \
.name = _bcmname, \
.keepalive = _keepalive, \
.num_nodes = ARRAY_SIZE(((struct qcom_icc_node *[]){ __VA_ARGS__ })), \
.nodes = { __VA_ARGS__ }, \
}
struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name);
void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
int qcom_icc_bcm_voter_commit(struct bcm_voter *voter);

10
drivers/interconnect/qcom/icc-rpmh.h
View File

@ -120,16 +120,6 @@ struct qcom_icc_desc {
size_t num_bcms;
};
#define DEFINE_QNODE(_name, _id, _channels, _buswidth, ...) \
static struct qcom_icc_node _name = { \
.id = _id, \
.name = #_name, \
.channels = _channels, \
.buswidth = _buswidth, \
.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
.links = { __VA_ARGS__ }, \
}
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
int qcom_icc_set(struct icc_node *src, struct icc_node *dst);

1611
drivers/interconnect/qcom/sc7180.c
View File

File diff suppressed because it is too large Load Diff

1384
drivers/interconnect/qcom/sdm670.c
View File

File diff suppressed because it is too large Load Diff

1653
drivers/interconnect/qcom/sdm845.c
View File

File diff suppressed because it is too large Load Diff

841
drivers/interconnect/qcom/sdx55.c
View File

@ -19,86 +19,769 @@
#include "icc-rpmh.h"
#include "sdx55.h"
DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0);
DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC);
DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVICE_SNOC);
DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP);
DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE_0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_TLMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_SLAVE_PCIE_0);
DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP);
DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCIE_0);
DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4);
DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0);
DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC);
DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4);
DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4);
DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4);
DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4);
DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4);
DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4);
DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4);
DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4);
DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4);
DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4);
DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4);
DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4);
DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4);
DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4);
DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4);
DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4);
DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4);
DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4);
DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_CFG);
DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4);
DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4);
DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4);
DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4);
DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4);
DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4);
DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC_SNOC);
DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MASTER_SNOC_GC_MEM_NOC);
DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8);
DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4);
DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8);
DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8);
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SDX55_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_EBI_CH0 },
};
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg);
DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie);
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);
DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);
DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm);
DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic);
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg);
DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto);
DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie);
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3,
&qns_aggre_noc);
DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr);
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc);
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie);
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv);
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
.id = SDX55_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX55_SLAVE_LLCC,
SDX55_SLAVE_MEM_NOC_SNOC,
SDX55_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SDX55_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_LLCC },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
.id = SDX55_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX55_SLAVE_LLCC,
SDX55_SLAVE_MEM_NOC_SNOC,
SDX55_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.id = SDX55_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
.id = SDX55_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SDX55_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 28,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = SDX55_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 5,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP,
SDX55_SLAVE_AUDIO
},
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
.id = SDX55_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_SLAVE_SERVICE_SNOC },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
.id = SDX55_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
.num_links = 3,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP
},
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = SDX55_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 30,
.links = { SDX55_SLAVE_PCIE_0,
SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QDSS_STM,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_USB3,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_APPSS,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
};
static struct qcom_icc_node qnm_ipa = {
.name = "qnm_ipa",
.id = SDX55_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 27,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_QDSS_STM,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
.id = SDX55_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 29,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_TLMM,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QDSS_STM,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_APPSS,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
.id = SDX55_MASTER_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_PCIE_0 },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SDX55_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP
},
};
static struct qcom_icc_node xm_emac = {
.name = "xm_emac",
.id = SDX55_MASTER_EMAC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node xm_ipa2pcie_slv = {
.name = "xm_ipa2pcie_slv",
.id = SDX55_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_PCIE_0 },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
.id = SDX55_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
.id = SDX55_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 28,
.links = { SDX55_SLAVE_SNOC_CFG,
SDX55_SLAVE_EMAC_CFG,
SDX55_SLAVE_USB3,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_SPMI_FETCHER,
SDX55_SLAVE_QDSS_CFG,
SDX55_SLAVE_PDM,
SDX55_SLAVE_SNOC_MEM_NOC_GC,
SDX55_SLAVE_TCSR,
SDX55_SLAVE_CNOC_DDRSS,
SDX55_SLAVE_SPMI_VGI_COEX,
SDX55_SLAVE_QPIC,
SDX55_SLAVE_OCIMEM,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_USB3_PHY_CFG,
SDX55_SLAVE_AOP,
SDX55_SLAVE_BLSP_1,
SDX55_SLAVE_SDCC_1,
SDX55_SLAVE_CNOC_MSS,
SDX55_SLAVE_PCIE_PARF,
SDX55_SLAVE_ECC_CFG,
SDX55_SLAVE_AUDIO,
SDX55_SLAVE_AOSS,
SDX55_SLAVE_PRNG,
SDX55_SLAVE_CRYPTO_0_CFG,
SDX55_SLAVE_TCU,
SDX55_SLAVE_CLK_CTL,
SDX55_SLAVE_IMEM_CFG
},
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SDX55_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 5,
.links = { SDX55_SLAVE_AOSS,
SDX55_SLAVE_IPA_CFG,
SDX55_SLAVE_ANOC_SNOC,
SDX55_SLAVE_AOP,
SDX55_SLAVE_AUDIO
},
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.id = SDX55_MASTER_USB3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = SDX55_SLAVE_EBI_CH0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = SDX55_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX55_SLAVE_EBI_CH0 },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
.id = SDX55_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_MEM_NOC_SNOC },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
.id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC },
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
.id = SDX55_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.id = SDX55_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.id = SDX55_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.id = SDX55_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_blsp1 = {
.name = "qhs_blsp1",
.id = SDX55_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = SDX55_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
.id = SDX55_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
.id = SDX55_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ecc_cfg = {
.name = "qhs_ecc_cfg",
.id = SDX55_SLAVE_ECC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_emac_cfg = {
.name = "qhs_emac_cfg",
.id = SDX55_SLAVE_EMAC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = SDX55_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.id = SDX55_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = SDX55_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_parf = {
.name = "qhs_pcie_parf",
.id = SDX55_SLAVE_PCIE_PARF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = SDX55_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.id = SDX55_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = SDX55_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.id = SDX55_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.id = SDX55_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
.id = SDX55_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX55_MASTER_SNOC_CFG },
};
static struct qcom_icc_node qhs_spmi_fetcher = {
.name = "qhs_spmi_fetcher",
.id = SDX55_SLAVE_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.id = SDX55_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = SDX55_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = SDX55_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.id = SDX55_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
.id = SDX55_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_aggre_noc = {
.name = "qns_aggre_noc",
.id = SDX55_SLAVE_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_ANOC_SNOC },
};
static struct qcom_icc_node qns_snoc_memnoc = {
.name = "qns_snoc_memnoc",
.id = SDX55_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX55_MASTER_SNOC_GC_MEM_NOC },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = SDX55_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
.id = SDX55_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
.id = SDX55_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = SDX55_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = SDX55_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_llcc },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_pn0 = {
.name = "PN0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qhm_snoc_cfg },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xm_apps_rdwr },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qns_memnoc_snoc, &qns_sys_pcie },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_snoc_memnoc },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxs_imem },
};
static struct qcom_icc_bcm bcm_pn1 = {
.name = "PN1",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xm_sdc1 },
};
static struct qcom_icc_bcm bcm_pn2 = {
.name = "PN2",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_qdss_stm },
};
static struct qcom_icc_bcm bcm_pn3 = {
.name = "PN3",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qhm_blsp1, &qhm_qpic },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_sys_tcu_cfg },
};
static struct qcom_icc_bcm bcm_pn5 = {
.name = "PN5",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_pcie },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
.num_nodes = 5,
.nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qhm_qdss_bam, &xm_qdss_etr },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_memnoc },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_memnoc_pcie },
};
static struct qcom_icc_bcm bcm_sn11 = {
.name = "SN11",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_mc0,

828
drivers/interconnect/qcom/sdx65.c
View File

@ -15,82 +15,760 @@
#include "icc-rpmh.h"
#include "sdx65.h"
DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1);
DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC);
DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU);
DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC);
DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU);
DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU);
DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0);
DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0);
DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU);
DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC);
DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4);
DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC);
DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC);
DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4);
DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4);
DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4);
DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4);
DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4);
DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4);
DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4);
DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4);
DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4);
DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4);
DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4);
DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4);
DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4);
DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4);
DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4);
DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4);
DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG);
DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4);
DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4);
DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4);
DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4);
DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4);
DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4);
DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC);
DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC);
DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8);
DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4);
DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8);
DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8);
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SDX65_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_EBI1 },
};
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc);
DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);
DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);
DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic);
DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc);
DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm);
DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg);
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie);
DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr);
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc);
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc);
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie);
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv);
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
.id = SDX65_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX65_SLAVE_LLCC,
SDX65_SLAVE_MEM_NOC_SNOC,
SDX65_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SDX65_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_SLAVE_LLCC },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
.id = SDX65_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX65_SLAVE_LLCC,
SDX65_SLAVE_MEM_NOC_SNOC,
SDX65_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.id = SDX65_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
.id = SDX65_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SDX65_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_TCU
},
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = SDX65_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 4,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_ANOC_SNOC
},
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
.id = SDX65_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_SERVICE_SNOC },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
.id = SDX65_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
.num_links = 2,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_ANOC_SNOC
},
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = SDX65_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 29,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_APPSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_PCIE_0,
SDX65_SLAVE_QDSS_STM,
SDX65_SLAVE_TCU
},
};
static struct qcom_icc_node qnm_ipa = {
.name = "qnm_ipa",
.id = SDX65_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_PCIE_0,
SDX65_SLAVE_QDSS_STM
},
};
static struct qcom_icc_node qnm_memnoc = {
.name = "qnm_memnoc",
.id = SDX65_MASTER_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 27,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_APPSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_QDSS_STM,
SDX65_SLAVE_TCU
},
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
.id = SDX65_MASTER_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_PCIE_0 },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SDX65_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_ANOC_SNOC
},
};
static struct qcom_icc_node xm_ipa2pcie_slv = {
.name = "xm_ipa2pcie_slv",
.id = SDX65_MASTER_IPA_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_PCIE_0 },
};
static struct qcom_icc_node xm_pcie = {
.name = "xm_pcie",
.id = SDX65_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
.id = SDX65_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_TCU
},
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SDX65_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 4,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_ANOC_SNOC
},
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.id = SDX65_MASTER_USB3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = SDX65_SLAVE_EBI1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = SDX65_SLAVE_LLCC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_MASTER_LLCC },
};
static struct qcom_icc_node qns_memnoc_snoc = {
.name = "qns_memnoc_snoc",
.id = SDX65_SLAVE_MEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_MASTER_MEM_NOC_SNOC },
};
static struct qcom_icc_node qns_sys_pcie = {
.name = "qns_sys_pcie",
.id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.id = SDX65_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.id = SDX65_SLAVE_APPSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.id = SDX65_SLAVE_AUDIO,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_blsp1 = {
.name = "qhs_blsp1",
.id = SDX65_SLAVE_BLSP_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = SDX65_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
.id = SDX65_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
.id = SDX65_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ecc_cfg = {
.name = "qhs_ecc_cfg",
.id = SDX65_SLAVE_ECC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = SDX65_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.id = SDX65_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = SDX65_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pcie_parf = {
.name = "qhs_pcie_parf",
.id = SDX65_SLAVE_PCIE_PARF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = SDX65_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.id = SDX65_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = SDX65_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.id = SDX65_SLAVE_QPIC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.id = SDX65_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
.id = SDX65_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_MASTER_SNOC_CFG },
};
static struct qcom_icc_node qhs_spmi_fetcher = {
.name = "qhs_spmi_fetcher",
.id = SDX65_SLAVE_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.id = SDX65_SLAVE_SPMI_VGI_COEX,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = SDX65_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = SDX65_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.id = SDX65_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_phy = {
.name = "qhs_usb3_phy",
.id = SDX65_SLAVE_USB3_PHY_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_aggre_noc = {
.name = "qns_aggre_noc",
.id = SDX65_SLAVE_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SDX65_MASTER_ANOC_SNOC },
};
static struct qcom_icc_node qns_snoc_memnoc = {
.name = "qns_snoc_memnoc",
.id = SDX65_SLAVE_SNOC_MEM_NOC_GC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_MASTER_SNOC_GC_MEM_NOC },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = SDX65_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
.id = SDX65_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_pcie = {
.name = "xs_pcie",
.id = SDX65_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = SDX65_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = SDX65_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_pn0 = {
.name = "PN0",
.keepalive = true,
.num_nodes = 26,
.nodes = { &qhm_snoc_cfg,
&qhs_aoss,
&qhs_apss,
&qhs_audio,
&qhs_blsp1,
&qhs_clk_ctl,
&qhs_crypto0_cfg,
&qhs_ddrss_cfg,
&qhs_ecc_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mss_cfg,
&qhs_pcie_parf,
&qhs_pdm,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qpic,
&qhs_sdc1,
&qhs_snoc_cfg,
&qhs_spmi_fetcher,
&qhs_spmi_vgi_coex,
&qhs_tcsr,
&qhs_tlmm,
&qhs_usb3,
&qhs_usb3_phy,
&srvc_snoc
},
};
static struct qcom_icc_bcm bcm_pn1 = {
.name = "PN1",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xm_sdc1 },
};
static struct qcom_icc_bcm bcm_pn2 = {
.name = "PN2",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
};
static struct qcom_icc_bcm bcm_pn3 = {
.name = "PN3",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qhm_blsp1, &qhm_qpic },
};
static struct qcom_icc_bcm bcm_pn4 = {
.name = "PN4",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_llcc },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_memnoc_snoc },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xm_apps_rdwr },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_snoc_memnoc },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxs_imem },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_qdss_stm },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_sys_tcu_cfg },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_pcie },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qhm_qdss_bam, &xm_qdss_etr },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
.num_nodes = 4,
.nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_memnoc },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_memnoc_pcie },
};
static struct qcom_icc_bcm bcm_sn10 = {
.name = "SN10",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_mc0,

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drivers/interconnect/qcom/sm6350.c
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drivers/interconnect/qcom/sm8150.c
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drivers/interconnect/qcom/sm8250.c
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drivers/interconnect/qcom/sm8350.c
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