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mvebu dt64 for 6.9 (part 1)

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Add mmc support for AC5
 Reorder crypto interrupts on Armada 3720
 Use the correct thermal coefficients for the Armada AP807 dies
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Merge tag 'mvebu-dt64-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt

mvebu dt64 for 6.9 (part 1)

Add mmc support for AC5
Reorder crypto interrupts on Armada 3720
Use the correct thermal coefficients for the Armada AP807 dies

* tag 'mvebu-dt64-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: armada-ap807: update thermal compatible
  arm64: dts: marvell: reorder crypto interrupts on Armada SoCs
  arm64: dts: ac5: add mmc node and clock

Link: https://lore.kernel.org/r/87a5nihr8g.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-04 08:28:50 +01:00
commit 3a591d5f44
5 changed files with 47 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
View File

@ -77,7 +77,6 @@ soc {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
internal-regs@7f000000 {
#address-cells = <1>;
@ -204,6 +203,30 @@ gpio1: gpio@18140 {
};
};
mmc_dma: bus@80500000 {
compatible = "simple-bus";
ranges;
#address-cells = <0x2>;
#size-cells = <0x2>;
reg = <0x0 0x80500000 0x0 0x100000>;
dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>;
dma-coherent;
sdhci: mmc@805c0000 {
compatible = "marvell,ac5-sdhci",
"marvell,armada-ap806-sdhci";
reg = <0x0 0x805c0000 0x0 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&emmc_clock>, <&cnm_clock>;
clock-names = "core", "axi";
bus-width = <8>;
non-removable;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
};
};
/*
* Dedicated section for devices behind 32bit controllers so we
* can configure specific DMA mapping for them
@ -335,5 +358,11 @@ nand_clock: nand-clock {
#clock-cells = <0>;
clock-frequency = <400000000>;
};
emmc_clock: emmc-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
};

4
arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts
View File

@ -99,3 +99,7 @@ parition@2 {
};
};
};
&sdhci {
status = "okay";
};

10
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -431,14 +431,14 @@ xor11 {
crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97ies";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2",
"ring3", "eip", "mem";
clocks = <&nb_periph_clk 15>;
};

3
arch/arm64/boot/dts/marvell/armada-ap807.dtsi
View File

@ -33,3 +33,6 @@ &ap_sdhci0 {
"marvell,armada-ap806-sdhci"; /* Backward compatibility */
};
&ap_thermal {
compatible = "marvell,armada-ap807-thermal";
};

10
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
View File

@ -511,14 +511,14 @@ CP11X_LABEL(sdhci0): mmc@780000 {
CP11X_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
<88 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
<92 IRQ_TYPE_LEVEL_HIGH>,
<87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3",
"eip", "mem";
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 26>,
<&CP11X_LABEL(clk) 1 17>;