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dt-bindings: clock: qcom, dispcc-sm6125: Allow power-domains property

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On SM6125 the dispcc block is gated behind VDDCX: allow this domain to
be configured.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/548970/
Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-6-a3f287dd6c07@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Marijn Suijten 2023-07-23 18:08:44 +02:00 committed by Dmitry Baryshkov
parent 3b3e71f07d
commit 3a06fa8e51
1 changed files with 16 additions and 0 deletions
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16
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
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@ -48,6 +48,16 @@ properties:
'#power-domain-cells':
const: 1
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing the power domain's performance point.
maxItems: 1
reg:
maxItems: 1
@ -65,9 +75,11 @@ examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@5f00000 {
compatible = "qcom,sm6125-dispcc";
reg = <0x5f00000 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
@ -84,6 +96,10 @@ examples:
"dp_phy_pll_vco_div_clk",
"cfg_ahb_clk",
"gcc_disp_gpll0_div_clk_src";
required-opps = <&rpmhpd_opp_ret>;
power-domains = <&rpmpd SM6125_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};