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i.MX clock changes for 5.19
- Add 27 MHz phy PLL ref clock - Add mcore_booted module parameter to tell kernel M core has already booted - Remove snvs clock - Add bindings for i.MX8MN GPT - Add check for kcalloc - Fix for a potential memory leak in __imx_clk_gpr_sync - Add DISP2 pixel clock for i.MX8MP - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage - Add clkout1/2 for i.MX8MP - Fix parent clock of ubs_root_clk for i.MX8MP -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdRlgxHYCb3ovKt456LNSLBEEo7YFAmKDYhQACgkQ6LNSLBEE o7bG3Q//QW2oyDfkTf5dc+y01N4+tgS9K9ZUdnFyWuliXIjnRlrM6i2kNfLyqbkY l22GVo+Q0EcG5TmQaD5FHaY30jpfcUI7Bgcmd9Pu8kSWmmIEQBSK0/5xcmS3qPPH Or78MIjxTmMEbsQy4ejaqDoJfFyRqJ7CN7ZpBKrcftAx58v1fTeKpdJUfIpQPhOM s740Vt2vFqK0cyoXdq5AL6FmDl4IUO2ya3rIXWd7+1J95HeM3yzA+UhpgXWDvKnv vi8nEbTUaVtLPn04o+5eT77cXjY6F6PcEn2DEC3naS9tumKW59Dp6dqDOsEANxDO SsgTPQWaEjifNSyULbZkpeacJ5M2eufsU330oQdur2WoJWYS+n/UAdfvmbUu1uEI Rg3xVo5MvBiFgHF890Yj20tdZyv2/bYXhMVvVPu9jt11LjTFYEfc04sQfdfx8kCH fHEJ53BxbBNsYibChIK9Q/Cm66SfBkfxmZ/3gXBLsf0WL5DKtidyO5fK0VyLxjLk S3ZhCoHgekxWu75xqxKLAUxLIGEVFk+AY+qEz7g2ZHks3Efz4L8dyTJ7v7uwmQi1 wuOkYsJWUU6pIqvDNytEDLkBsuy0XAYiDxP0k9fDFfj6vfaLOCJZJlA+mDv/qj8H VsvluQui682wsTJ02+jkjXUrYq45bxo1Al6j64qtIfo7QsZuC0I= =2CUT -----END PGP SIGNATURE----- Merge tag 'clk-imx-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Add 27 MHz phy PLL ref clock - Add mcore_booted module parameter to tell kernel M core has already booted - Remove snvs clock - Add bindings for i.MX8MN GPT - Add check for kcalloc - Fix for a potential memory leak in __imx_clk_gpr_sync - Add DISP2 pixel clock for i.MX8MP - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage - Add clkout1/2 for i.MX8MP - Fix parent clock of ubs_root_clk for i.MX8MP * tag 'clk-imx-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx8mp: fix usb_root_clk parent clk: imx8mp: add clkout1/2 support clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: imx8mp: Add DISP2 pixel clock clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu() clk: imx: Add check for kcalloc clk: imx8mn: add GPT support dt-bindings: imx: add clock bindings for i.MX8MN GPT clk: imx: Remove the snvs clock clk: imx8m: check mcore_booted before register clk clk: imx: add mcore_booted module paratemter clk: imx8mq: add 27m phy pll ref clock
This commit is contained in:
Stephen Boyd
commit
3972b152e3
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@ -178,7 +178,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
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unsigned long flags)
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{
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struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
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struct clk_hw *div_hw, *gate_hw;
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struct clk_hw *div_hw, *gate_hw = NULL;
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struct clk_divider *div = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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@ -223,14 +223,17 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
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div->lock = &imx_ccm_lock;
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div->flags = CLK_DIVIDER_ROUND_CLOSEST;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto fail;
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/* skip registering the gate ops if M4 is enabled */
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if (!mcore_booted) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto fail;
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gate_hw = &gate->hw;
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gate->reg = reg;
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gate->bit_idx = PCG_CGC_SHIFT;
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gate->lock = &imx_ccm_lock;
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gate_hw = &gate->hw;
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gate->reg = reg;
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gate->bit_idx = PCG_CGC_SHIFT;
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gate->lock = &imx_ccm_lock;
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}
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, mux_ops, div_hw,
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@ -782,7 +782,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
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hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
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hws[IMX7D_OCOTP_CLK] = imx_clk_hw_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
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hws[IMX7D_SNVS_CLK] = imx_clk_hw_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
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hws[IMX7D_MU_ROOT_CLK] = imx_clk_hw_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0);
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hws[IMX7D_CAAM_CLK] = imx_clk_hw_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
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hws[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_hw_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
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@ -560,7 +560,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
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hws[IMX8MM_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
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hws[IMX8MM_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
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hws[IMX8MM_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
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hws[IMX8MM_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
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hws[IMX8MM_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
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hws[IMX8MM_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
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hws[IMX8MM_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
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@ -639,6 +638,8 @@ static struct platform_driver imx8mm_clk_driver = {
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},
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};
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module_platform_driver(imx8mm_clk_driver);
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module_param(mcore_booted, bool, S_IRUGO);
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MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
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MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
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MODULE_DESCRIPTION("NXP i.MX8MM clock driver");
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@ -227,6 +227,30 @@ static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys
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"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
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"sys_pll1_80m", "video_pll1_out", };
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static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
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"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
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"audio_pll1_out", "clk_ext1", };
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static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
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"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
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"audio_pll1_out", "clk_ext1", };
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static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
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"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
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"audio_pll1_out", "clk_ext1", };
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static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
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"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
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"audio_pll1_out", "clk_ext1", };
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static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
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"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
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"audio_pll1_out", "clk_ext1", };
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static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
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"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
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"audio_pll1_out", "clk_ext1", };
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static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
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"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
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"sys_pll1_80m", "sys_pll2_166m", };
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@ -476,6 +500,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
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hws[IMX8MN_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
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hws[IMX8MN_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
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hws[IMX8MN_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
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hws[IMX8MN_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mn_gpt1_sels, base + 0xb580);
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hws[IMX8MN_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mn_gpt2_sels, base + 0xb600);
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hws[IMX8MN_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mn_gpt3_sels, base + 0xb680);
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hws[IMX8MN_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mn_gpt4_sels, base + 0xb700);
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hws[IMX8MN_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mn_gpt5_sels, base + 0xb780);
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hws[IMX8MN_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mn_gpt6_sels, base + 0xb800);
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hws[IMX8MN_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
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hws[IMX8MN_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
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hws[IMX8MN_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
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@ -501,6 +531,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
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hws[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
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hws[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
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hws[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
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hws[IMX8MN_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
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hws[IMX8MN_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", base + 0x4110, 0);
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hws[IMX8MN_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", base + 0x4120, 0);
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hws[IMX8MN_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", base + 0x4130, 0);
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hws[IMX8MN_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", base + 0x4140, 0);
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hws[IMX8MN_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", base + 0x4150, 0);
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hws[IMX8MN_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
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hws[IMX8MN_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
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hws[IMX8MN_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
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@ -522,7 +558,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
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hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
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hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
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hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
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hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
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hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
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hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
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hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
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@ -549,6 +584,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
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hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
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hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
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hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
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hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
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hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
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@ -594,6 +631,8 @@ static struct platform_driver imx8mn_clk_driver = {
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},
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};
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module_platform_driver(imx8mn_clk_driver);
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module_param(mcore_booted, bool, S_IRUGO);
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MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
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MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
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MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
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@ -358,7 +358,7 @@ static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_p
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"clk_ext2", "audio_pll2_out",
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"video_pll1_out", };
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static const char * const imx8mp_media_disp1_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
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static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
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"audio_pll1_out", "sys_pll1_800m",
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"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
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@ -399,6 +399,11 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au
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static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
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static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
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"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
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"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
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"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
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static struct clk_hw **hws;
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static struct clk_hw_onecell_data *clk_hw_data;
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@ -504,6 +509,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
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hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
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hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
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hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4,
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imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
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hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4);
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hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8);
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hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4,
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imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
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hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
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hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
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hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
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hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
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hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
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@ -538,6 +552,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
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hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
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hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
|
||||
hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
|
||||
hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300);
|
||||
|
||||
hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
|
||||
|
||||
|
|
@ -600,7 +615,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
|
||||
hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
|
||||
hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
|
||||
hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00);
|
||||
hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00);
|
||||
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
|
||||
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
|
||||
hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80);
|
||||
|
|
@ -654,12 +669,11 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
|
||||
hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
|
||||
hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
|
||||
hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0);
|
||||
hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
|
||||
hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
|
||||
hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
|
||||
hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
|
||||
hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0);
|
||||
hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0);
|
||||
hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
|
||||
hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
|
||||
hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);
|
||||
|
|
@ -721,6 +735,8 @@ static struct platform_driver imx8mp_clk_driver = {
|
|||
},
|
||||
};
|
||||
module_platform_driver(imx8mp_clk_driver);
|
||||
module_param(mcore_booted, bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
|
||||
|
||||
MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX8MP clock driver");
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ static u32 share_count_sai6;
|
|||
static u32 share_count_dcss;
|
||||
static u32 share_count_nand;
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
|
||||
static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
|
|
@ -557,7 +557,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MQ_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MQ_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MQ_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MQ_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
|
|
@ -632,6 +631,8 @@ static struct platform_driver imx8mq_clk_driver = {
|
|||
},
|
||||
};
|
||||
module_platform_driver(imx8mq_clk_driver);
|
||||
module_param(mcore_booted, bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
|
||||
|
||||
MODULE_AUTHOR("Abel Vesa <abel.vesa@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX8MQ clock driver");
|
||||
|
|
|
|||
|
|
@ -528,7 +528,7 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
|
|||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret) {
|
||||
pm_genpd_remove_device(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
|
@ -837,8 +837,10 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na
|
|||
if (!clk_node)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
if (!imx_scu_clk_is_valid(rsrc_id))
|
||||
if (!imx_scu_clk_is_valid(rsrc_id)) {
|
||||
kfree(clk_node);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
if (!clk) {
|
||||
|
|
|
|||
|
|
@ -17,6 +17,9 @@
|
|||
DEFINE_SPINLOCK(imx_ccm_lock);
|
||||
EXPORT_SYMBOL_GPL(imx_ccm_lock);
|
||||
|
||||
bool mcore_booted;
|
||||
EXPORT_SYMBOL_GPL(mcore_booted);
|
||||
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
|
@ -173,6 +176,8 @@ void imx_register_uart_clocks(unsigned int clk_count)
|
|||
int i;
|
||||
|
||||
imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!imx_uart_clocks)
|
||||
return;
|
||||
|
||||
if (!of_stdout)
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
|
||||
extern spinlock_t imx_ccm_lock;
|
||||
extern bool mcore_booted;
|
||||
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
|
|
|
|||
|
|
@ -243,6 +243,20 @@
|
|||
|
||||
#define IMX8MN_CLK_M7_CORE 221
|
||||
|
||||
#define IMX8MN_CLK_END 222
|
||||
#define IMX8MN_CLK_GPT_3M 222
|
||||
#define IMX8MN_CLK_GPT1 223
|
||||
#define IMX8MN_CLK_GPT1_ROOT 224
|
||||
#define IMX8MN_CLK_GPT2 225
|
||||
#define IMX8MN_CLK_GPT2_ROOT 226
|
||||
#define IMX8MN_CLK_GPT3 227
|
||||
#define IMX8MN_CLK_GPT3_ROOT 228
|
||||
#define IMX8MN_CLK_GPT4 229
|
||||
#define IMX8MN_CLK_GPT4_ROOT 230
|
||||
#define IMX8MN_CLK_GPT5 231
|
||||
#define IMX8MN_CLK_GPT5_ROOT 232
|
||||
#define IMX8MN_CLK_GPT6 233
|
||||
#define IMX8MN_CLK_GPT6_ROOT 234
|
||||
|
||||
#define IMX8MN_CLK_END 235
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -317,8 +317,15 @@
|
|||
#define IMX8MP_CLK_AUDIO_AXI 310
|
||||
#define IMX8MP_CLK_HSIO_AXI 311
|
||||
#define IMX8MP_CLK_MEDIA_ISP 312
|
||||
#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
|
||||
#define IMX8MP_CLK_CLKOUT1_SEL 314
|
||||
#define IMX8MP_CLK_CLKOUT1_DIV 315
|
||||
#define IMX8MP_CLK_CLKOUT1 316
|
||||
#define IMX8MP_CLK_CLKOUT2_SEL 317
|
||||
#define IMX8MP_CLK_CLKOUT2_DIV 318
|
||||
#define IMX8MP_CLK_CLKOUT2 319
|
||||
|
||||
#define IMX8MP_CLK_END 313
|
||||
#define IMX8MP_CLK_END 320
|
||||
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user