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drm/panfrost: Introduce a reset lock
In order to avoid accessing HW register while a reset is ongoing, a read/write semaphore that envelopes the reset sequence will help driver entry points avoid racing with it. For now, the only such racy entry point is the ioctl that returns the current GPU timestamp. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20261012-claude-fixes-v15-14-bc0a6c498553@collabora.com Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
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@ -509,6 +509,8 @@ bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
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void panfrost_device_reset(struct panfrost_device *pfdev, bool enable_job_int)
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{
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guard(rwsem_write)(&pfdev->reset.lock);
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panfrost_gpu_soft_reset(pfdev);
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panfrost_gpu_power_on(pfdev);
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@ -165,6 +165,7 @@ struct panfrost_device {
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struct {
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struct workqueue_struct *wq;
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struct work_struct work;
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struct rw_semaphore lock;
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atomic_t pending;
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} reset;
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@ -41,9 +41,12 @@ static int panfrost_ioctl_query_timestamp(struct panfrost_device *pfdev,
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if (ret)
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return ret;
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panfrost_cycle_counter_get(pfdev);
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*arg = panfrost_timestamp_read(pfdev);
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panfrost_cycle_counter_put(pfdev);
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/* We should not read timestamp register while the GPU is being reset */
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scoped_guard(rwsem_read, &pfdev->reset.lock) {
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panfrost_cycle_counter_get(pfdev);
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*arg = panfrost_timestamp_read(pfdev);
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panfrost_cycle_counter_put(pfdev);
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}
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pm_runtime_put(pfdev->base.dev);
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return 0;
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@ -877,6 +877,7 @@ int panfrost_jm_init(struct panfrost_device *pfdev)
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INIT_WORK(&pfdev->reset.work, panfrost_reset_work);
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spin_lock_init(&js->job_lock);
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mutex_init(&pfdev->sched_lock);
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init_rwsem(&pfdev->reset.lock);
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js->irq = platform_get_irq_byname(to_platform_device(pfdev->base.dev), "job");
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if (js->irq < 0)
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