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clk: qcom: gcc-mdm9607: Drop incorrect apss_tcu_clk_src

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This clock does not exist on the specified address on MDM9607.
Reading/writing the registers always results in 0 or crashes. The math in
the frequency table is also broken. GPLL2 on MDM9607 runs at 480 MHz, so:

 - F(155000000, P_GPLL2, 6, 0, 0), // 480 MHz/6 = 80 MHz, not 155 MHz
 - F(310000000, P_GPLL2, 3, 0, 0), // 480 MHz/3 = 160 MHz, not 310 MHz

Presumably, this definition was mistakenly copied as-is from gcc-msm8916
(which uses 930 MHz for GPLL2). There are no branch consumers of this root
clock inside gcc-mdm9607 (notably, gcc_apss_tcu_clk has bimc_ddr_clk_src as
parent instead of this clock), so we can just drop it.

It seems like this clock does exist on this SoC on a different address, but
since there is no user and reference code for it, it is still better to
drop it.

Cc: stable@vger.kernel.org
Fixes: 48b7253264 ("clk: qcom: Add MDM9607 GCC driver")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20260706-qcom-clk-mdm9607-fixes-v2-6-745565101869@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Stephan Gerhold 2026-07-06 17:02:13 +02:00 committed by Bjorn Andersson
parent c99bc8e838
commit 38d06956f6
1 changed files with 0 additions and 35 deletions
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35
drivers/clk/qcom/gcc-mdm9607.c
View File

@ -158,20 +158,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
{ P_GPLL2, 3 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1_vote.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
@ -674,26 +660,6 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
},
};
static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
F(155000000, P_GPLL2, 6, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 apss_tcu_clk_src = {
.cmd_rcgr = 0x1207c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1_gpll2_map,
.freq_tbl = ftbl_gcc_apss_tcu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_gpll2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(57140000, P_GPLL0, 14, 0, 0),
@ -1512,7 +1478,6 @@ static struct clk_regmap *gcc_mdm9607_clocks[] = {
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,