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can: m_can: clean up CCCR reg defs, order by revs

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Ensures that the different CCCR regmasks for m_can revs 3.0.x, 3.1.x,
3.2.x and 3.3.x are clearly distinguishable. Removes incorrect
CCCR_CANFD define. Adds bit fields UTSU and WMM for rev 3.3.x, for
completeness.

Link: https://lore.kernel.org/r/20210504125123.500553-3-torin@maxiluxsystems.com
Signed-off-by: Torin Cooper-Bennun <torin@maxiluxsystems.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Torin Cooper-Bennun 2021-05-04 13:51:21 +01:00 committed by Marc Kleine-Budde
parent 20779943a0
commit 38395f302f
1 changed files with 13 additions and 10 deletions
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23
drivers/net/can/m_can/m_can.c
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@ -102,14 +102,6 @@ enum m_can_reg {
#define TEST_LBCK BIT(4)
/* CC Control Register(CCCR) */
#define CCCR_CMR_MASK GENMASK(11, 10)
#define CCCR_CMR_CANFD 0x1
#define CCCR_CMR_CANFD_BRS 0x2
#define CCCR_CMR_CAN 0x3
#define CCCR_CME_MASK GENMASK(9, 8)
#define CCCR_CME_CAN 0
#define CCCR_CME_CANFD 0x1
#define CCCR_CME_CANFD_BRS 0x2
#define CCCR_TXP BIT(14)
#define CCCR_TEST BIT(7)
#define CCCR_DAR BIT(6)
@ -119,14 +111,25 @@ enum m_can_reg {
#define CCCR_ASM BIT(2)
#define CCCR_CCE BIT(1)
#define CCCR_INIT BIT(0)
#define CCCR_CANFD BIT(4)
/* for version 3.0.x */
#define CCCR_CMR_MASK GENMASK(11, 10)
#define CCCR_CMR_CANFD 0x1
#define CCCR_CMR_CANFD_BRS 0x2
#define CCCR_CMR_CAN 0x3
#define CCCR_CME_MASK GENMASK(9, 8)
#define CCCR_CME_CAN 0
#define CCCR_CME_CANFD 0x1
#define CCCR_CME_CANFD_BRS 0x2
/* for version >=3.1.x */
#define CCCR_EFBI BIT(13)
#define CCCR_PXHD BIT(12)
#define CCCR_BRSE BIT(9)
#define CCCR_FDOE BIT(8)
/* only for version >=3.2.x */
/* for version >=3.2.x */
#define CCCR_NISO BIT(15)
/* for version >=3.3.x */
#define CCCR_WMM BIT(11)
#define CCCR_UTSU BIT(10)
/* Nominal Bit Timing & Prescaler Register (NBTP) */
#define NBTP_NSJW_MASK GENMASK(31, 25)