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drm/i915/pcode: rename GEN6_PCODE_DATA to match spec

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Variable naming of val and val1 should match register macro naming.
Historically, corresponding macros were named GEN6_PCODE_DATA and
GEN6_PCODE_DATA1.

Rename register macro GEN6_PCODE_DATA to GEN6_PCODE_DATA0 since spec
appended '0' to the register name. Rename val into val0 in functions
declaring val1 for both i915-specific and shared display code.

v4->v5
- clean changelog's versioning

v3->v4
- split i915 changes from xe (Jani)
- apply the rename to the read()'s signature as well (Sashiko)

v2->v3
- resolve conflict from rebase

v1->v2
- rebase onto drm-tip (Jani)

Bspec: 19978
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260828190956.2622350-2-michal.grzelak@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Michał Grzelak 2026-08-28 21:09:55 +02:00 committed by Jani Nikula
parent 442be3b2a7
commit 3802cbc4b4
8 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_parent.c
View File

@ -281,9 +281,9 @@ void intel_parent_pc8_unblock(struct intel_display *display)
}
/* pcode */
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1)
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val0, u32 *val1)
{
return display->parent->pcode->read(display->drm, mbox, val, val1);
return display->parent->pcode->read(display->drm, mbox, val0, val1);
}
int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms)

2
drivers/gpu/drm/i915/display/intel_parent.h
View File

@ -115,7 +115,7 @@ void intel_parent_pc8_block(struct intel_display *display);
void intel_parent_pc8_unblock(struct intel_display *display);
/* pcode */
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1);
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val0, u32 *val1);
int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms);
int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val);
int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,

2
drivers/gpu/drm/i915/gvt/handlers.c
View File

@ -1706,7 +1706,7 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
{
u32 value = *(u32 *)p_data;
u32 cmd = value & 0xff;
u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA0);
switch (cmd) {
case GEN9_PCODE_READ_MEM_LATENCY:

2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -697,7 +697,7 @@
#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_DATA0 _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
#define GEN6_PCODE_DATA1 _MMIO(0x13812C)

2
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@ -611,7 +611,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GEN6_UCGCTL1);
MMIO_D(GEN6_UCGCTL2);
MMIO_F(_MMIO(0x4f000), 0x90);
MMIO_D(GEN6_PCODE_DATA);
MMIO_D(GEN6_PCODE_DATA0);
MMIO_D(_MMIO(0x13812c));
MMIO_D(GEN7_ERR_INT);
MMIO_D(HSW_EDRAM_CAP);

14
drivers/gpu/drm/i915/intel_pcode.c
View File

@ -58,7 +58,7 @@ static int gen7_check_mailbox_status(u32 mbox)
}
static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
u32 *val, u32 *val1,
u32 *val0, u32 *val1,
int fast_timeout_us, int slow_timeout_ms,
bool is_read)
{
@ -73,7 +73,7 @@ static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
return -EAGAIN;
intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
intel_uncore_write_fw(uncore, GEN6_PCODE_DATA0, *val0);
intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
intel_uncore_write_fw(uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
@ -87,7 +87,7 @@ static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
return -ETIMEDOUT;
if (is_read)
*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
*val0 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA0);
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
@ -97,12 +97,12 @@ static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
return gen6_check_mailbox_status(mbox);
}
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val0, u32 *val1)
{
int err;
mutex_lock(&uncore->i915->sb_lock);
err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
err = __snb_pcode_rw(uncore, mbox, val0, val1, 500, 20, true);
mutex_unlock(&uncore->i915->sb_lock);
if (err) {
@ -278,11 +278,11 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
return err;
}
static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val0, u32 *val1)
{
struct drm_i915_private *i915 = to_i915(drm);
return snb_pcode_read(&i915->uncore, mbox, val, val1);
return snb_pcode_read(&i915->uncore, mbox, val0, val1);
}
static int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)

2
drivers/gpu/drm/i915/intel_pcode.h
View File

@ -11,7 +11,7 @@
struct drm_device;
struct intel_uncore;
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val0, u32 *val1);
int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, int timeout_ms);
#define snb_pcode_write(uncore, mbox, val) \
snb_pcode_write_timeout((uncore), (mbox), (val), 1)

2
include/drm/intel/display_parent_interface.h
View File

@ -179,7 +179,7 @@ struct intel_display_pc8_interface {
};
struct intel_display_pcode_interface {
int (*read)(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
int (*read)(struct drm_device *drm, u32 mbox, u32 *val0, u32 *val1);
int (*write)(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
int (*request)(struct drm_device *drm, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);