From 5ed8cdb56cd90859e0c7f269b4a7c2b1571419b2 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 14 Jul 2026 15:45:11 +0800 Subject: [PATCH 1/5] riscv: dts: thead: th1520: remove pclk for I2C1 The I2C1 node added previously to the th1520.dtsi file has two clocks set -- one "ref" clock (CLK_I2C1) and one "pclk" (CLK_PERI_APB_PCLK). However, the CLK_I2C1 clock is just a clock gate with the CLK_PERI_APB_PCLK clock as its input. In addition, when it's gated, reading registers from the I2C controller returns fixed value (the last read value) for all registers. These facts indicate that the CLK_I2C1 clock is the true APB clock fed into the I2C controller instead of a dedicated reference clock. Leave only the CLK_I2C1 clock as the `clocks` property of the I2C1 device node and remove `clock-names` property, which represents the I2C controller only takes a single clock both as the APB clock and the reference clock. Fixes: 2f60e3516330 ("riscv: dts: thead: Add TH1520 I2C1 controller") Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini Link: https://lore.kernel.org/r/20260714074515.1959352-2-zhengxingda@iscas.ac.cn Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 94932c51b7e3..db23624696b7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -415,8 +415,7 @@ i2c1: i2c@ffe7f24000 { compatible = "thead,th1520-i2c", "snps,designware-i2c"; reg = <0xff 0xe7f24000 0x0 0x4000>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>; - clock-names = "ref", "pclk"; + clocks = <&clk CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From b6e4c8fe4cbeb71365e579904fbd4cb6437ff278 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Tue, 14 Jul 2026 15:45:12 +0800 Subject: [PATCH 2/5] riscv: dts: thead: Add TH1520 I2C nodes Add nodes for the remaining five I2C controllers on the T-Head TH1520 RISCV SoC. Link: https://lore.kernel.org/r/20260714074515.1959352-3-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Thomas Bonnefille [Icenowy: rebase and reword commit message to exclude I2C1] Signed-off-by: Icenowy Zheng Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index db23624696b7..b01a94785d87 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -411,6 +411,16 @@ uart3: serial@ffe7f04000 { status = "disabled"; }; + i2c0: i2c@ffe7f20000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f20000 0x0 0x4000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@ffe7f24000 { compatible = "thead,th1520-i2c", "snps,designware-i2c"; reg = <0xff 0xe7f24000 0x0 0x4000>; @@ -421,6 +431,16 @@ i2c1: i2c@ffe7f24000 { status = "disabled"; }; + i2c4: i2c@ffe7f28000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f28000 0x0 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; @@ -519,6 +539,16 @@ padctrl0_apsys: pinctrl@ffec007000 { thead,pad-group = <3>; }; + i2c2: i2c@ffec00c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec00c000 0x0 0x4000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -530,6 +560,16 @@ uart2: serial@ffec010000 { status = "disabled"; }; + i2c3: i2c@ffec014000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec014000 0x0 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm: pwm@ffec01c000 { compatible = "thead,th1520-pwm"; reg = <0xff 0xec01c000 0x0 0x4000>; @@ -735,6 +775,16 @@ uart5: serial@fff7f0c000 { status = "disabled"; }; + i2c5: i2c@fff7f2c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xf7f2c000 0x0 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; From c8f71218e9ac1a01fd355eabe62957df17d13b83 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 14 Jul 2026 15:45:13 +0800 Subject: [PATCH 3/5] riscv: dts: thead: lpi4a: sort nodes Although "D", "H" and "I" are earlier in the alphabet than "P", the DPU, HDMI and I2C1 nodes were added after PADCTRL nodes in the Lichee Pi 4A device tree; in addition the PADCTRL1 node is placed before the PADCTRL0 one. Sort the nodes in this device tree. Link: https://lore.kernel.org/r/20260714074515.1959352-4-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Icenowy Zheng Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 72 +++++++++---------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index af6f25ebbf60..74b120c6b063 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -103,17 +103,31 @@ fan: pwm-fan { }; -&padctrl1_apsys { - i2c1_pins: i2c1-0 { - i2c-pins { - pins = "I2C1_SCL", "I2C1_SDA"; - function = "i2c"; - bias-pull-up = <2100>; - drive-strength = <7>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; +&dpu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + + ioexp2: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; }; }; @@ -153,17 +167,17 @@ rx-pins { }; }; -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - ioexp2: gpio@18 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; +&padctrl1_apsys { + i2c1_pins: i2c1-0 { + i2c-pins { + pins = "I2C1_SCL", "I2C1_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; }; }; @@ -179,20 +193,6 @@ &sdio1 { status = "okay"; }; -&dpu { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out_port { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; From 01ba55917c27161f8480adf17c1bb8c6f6b62a09 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 14 Jul 2026 15:45:14 +0800 Subject: [PATCH 4/5] riscv: dts: thead: Add IO labels for the IO expansion on I2C1 Add labels for GPIOs on the IO expansion chip on the I2C1 bus. Link: https://lore.kernel.org/r/20260714074515.1959352-5-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Emil Renner Berthing [Icenowy: Splitted off the patch adding all 3 IO expansions] Signed-off-by: Icenowy Zheng [fustini: align ioexp2 gpio-line-names with schematic] Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 74b120c6b063..5523957430ea 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -128,6 +128,14 @@ ioexp2: gpio@18 { reg = <0x18>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "", + "cam0_reset", + "cam1_reset", + "cam2_reset", + "wl_host_wake_dev", + "bt_resetn", + "", + "bt_host_wake_dev"; }; }; From 15d32aaf6300b832814a9930fdbd20efdbc9adcf Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 14 Jul 2026 15:45:15 +0800 Subject: [PATCH 5/5] riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the I2C0/1/3 busses. The I2C1 one is already added to the device tree, but the I2C0/3 ones are not yet added. Add device tree nodes for them. Link: https://lore.kernel.org/r/20260714074515.1959352-6-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Emil Renner Berthing [Icenowy: added commit description, enable SoC pull-up, remove I2C1 and aliases] Signed-off-by: Icenowy Zheng Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 5523957430ea..1eb575aa9a74 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -117,6 +117,23 @@ hdmi_out_con: endpoint { }; }; +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + ioexp1: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "cam0_dvdd12", + "cam0_avdd28", + "cam0_dovdd18"; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -139,6 +156,28 @@ ioexp2: gpio@18 { }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + ioexp3: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "tp0_rst", + "", + "", + "vcc5v_usb", + "vdd28_tp0", + "vdd33_lcd0", + "vdd18_lcd0", + "lcd0_reset"; + }; +}; + &padctrl0_apsys { fan_pins: fan-0 { pwm1-pins { @@ -152,6 +191,18 @@ pwm1-pins { }; }; + i2c3_pins: i2c3-0 { + i2c-pins { + pins = "I2C3_SCL", "I2C3_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins = "UART0_TXD"; @@ -176,6 +227,18 @@ rx-pins { }; &padctrl1_apsys { + i2c0_pins: i2c0-0 { + i2c-pins { + pins = "I2C0_SCL", "I2C0_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + i2c1_pins: i2c1-0 { i2c-pins { pins = "I2C1_SCL", "I2C1_SDA";