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drm/amdgpu: finish wiring up sid.h in DCE6

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For coherence with DCE8 et DCE10, add or move some values under sid.h
and remove duplicated from si_enums.h.

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alexandre Demers 2025-03-09 12:48:52 -04:00 committed by Alex Deucher
parent 42c854b8fb
commit 37c890d831
3 changed files with 55 additions and 43 deletions
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63
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
View File

@ -41,6 +41,7 @@
#include "amdgpu_display.h"
#include "dce_v6_0.h"
#include "sid.h"
#include "bif/bif_3_0_d.h"
#include "bif/bif_3_0_sh_mask.h"
@ -65,31 +66,31 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static const u32 crtc_offsets[6] =
{
SI_CRTC0_REGISTER_OFFSET,
SI_CRTC1_REGISTER_OFFSET,
SI_CRTC2_REGISTER_OFFSET,
SI_CRTC3_REGISTER_OFFSET,
SI_CRTC4_REGISTER_OFFSET,
SI_CRTC5_REGISTER_OFFSET
CRTC0_REGISTER_OFFSET,
CRTC1_REGISTER_OFFSET,
CRTC2_REGISTER_OFFSET,
CRTC3_REGISTER_OFFSET,
CRTC4_REGISTER_OFFSET,
CRTC5_REGISTER_OFFSET
};
static const u32 hpd_offsets[] =
{
mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
HPD0_REGISTER_OFFSET,
HPD1_REGISTER_OFFSET,
HPD2_REGISTER_OFFSET,
HPD3_REGISTER_OFFSET,
HPD4_REGISTER_OFFSET,
HPD5_REGISTER_OFFSET
};
static const uint32_t dig_offsets[] = {
SI_CRTC0_REGISTER_OFFSET,
SI_CRTC1_REGISTER_OFFSET,
SI_CRTC2_REGISTER_OFFSET,
SI_CRTC3_REGISTER_OFFSET,
SI_CRTC4_REGISTER_OFFSET,
SI_CRTC5_REGISTER_OFFSET,
CRTC0_REGISTER_OFFSET,
CRTC1_REGISTER_OFFSET,
CRTC2_REGISTER_OFFSET,
CRTC3_REGISTER_OFFSET,
CRTC4_REGISTER_OFFSET,
CRTC5_REGISTER_OFFSET,
(0x13830 - 0x7030) >> 2,
};
@ -1395,13 +1396,13 @@ static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
static const u32 pin_offsets[7] =
{
(0x1780 - 0x1780),
(0x1786 - 0x1780),
(0x178c - 0x1780),
(0x1792 - 0x1780),
(0x1798 - 0x1780),
(0x179d - 0x1780),
(0x17a4 - 0x1780),
AUD0_REGISTER_OFFSET,
AUD1_REGISTER_OFFSET,
AUD2_REGISTER_OFFSET,
AUD3_REGISTER_OFFSET,
AUD4_REGISTER_OFFSET,
AUD5_REGISTER_OFFSET,
AUD6_REGISTER_OFFSET,
};
static int dce_v6_0_audio_init(struct amdgpu_device *adev)
@ -2960,22 +2961,22 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
switch (crtc) {
case 0:
reg_block = SI_CRTC0_REGISTER_OFFSET;
reg_block = CRTC0_REGISTER_OFFSET;
break;
case 1:
reg_block = SI_CRTC1_REGISTER_OFFSET;
reg_block = CRTC1_REGISTER_OFFSET;
break;
case 2:
reg_block = SI_CRTC2_REGISTER_OFFSET;
reg_block = CRTC2_REGISTER_OFFSET;
break;
case 3:
reg_block = SI_CRTC3_REGISTER_OFFSET;
reg_block = CRTC3_REGISTER_OFFSET;
break;
case 4:
reg_block = SI_CRTC4_REGISTER_OFFSET;
reg_block = CRTC4_REGISTER_OFFSET;
break;
case 5:
reg_block = SI_CRTC5_REGISTER_OFFSET;
reg_block = CRTC5_REGISTER_OFFSET;
break;
default:
DRM_DEBUG("invalid crtc %d\n", crtc);

6
drivers/gpu/drm/amd/amdgpu/si_enums.h
View File

@ -121,12 +121,6 @@
#define CURSOR_UPDATE_LOCK (1 << 16)
#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
#define SI_CRTC0_REGISTER_OFFSET 0
#define SI_CRTC1_REGISTER_OFFSET 0x300
#define SI_CRTC2_REGISTER_OFFSET 0x2600
#define SI_CRTC3_REGISTER_OFFSET 0x2900
#define SI_CRTC4_REGISTER_OFFSET 0x2c00
#define SI_CRTC5_REGISTER_OFFSET 0x2f00
#define ES_AND_GS_AUTO 3
#define RADEON_PACKET_TYPE3 3

29
drivers/gpu/drm/amd/amdgpu/sid.h
View File

@ -1700,12 +1700,29 @@
//#dce stupp
/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
#define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/4
#define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 - 0x6df0)/4
#define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 - 0x6df0)/4
#define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 - 0x6df0)/4
#define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 - 0x6df0)/4
#define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 - 0x6df0)/4
#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4
#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4
#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4
#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4
#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4
#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4
/* hpd instance offsets */
#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
#define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
#define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
/* audio endpt instance offsets */
#define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
#define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
#define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
#define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
#define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
#define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
#define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
#define CURSOR_WIDTH 64
#define CURSOR_HEIGHT 64