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drm/msm: Use drm_gpuvm types more

Browse Source 
Most of the driver code doesn't need to reach in to msm specific fields,
so just use the drm_gpuvm/drm_gpuva types directly.  This should
hopefully improve commonality with other drivers and make the code
easier to understand.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Tested-by: Antonino Maniscalco <antomani103@gmail.com>
Reviewed-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/661483/
This commit is contained in:
Rob Clark 2025-06-29 13:12:58 -07:00 committed by Rob Clark
parent fe4952b5f2
commit 37889600f5
23 changed files with 175 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
View File

@ -113,7 +113,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
uint32_t *ptr, len;
int i, ret;
a2xx_gpummu_params(gpu->vm->mmu, &pt_base, &tran_error);
a2xx_gpummu_params(to_msm_vm(gpu->vm)->mmu, &pt_base, &tran_error);
DBG("%s", gpu->name);
@ -466,11 +466,11 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)
return state;
}
static struct msm_gem_vm *
static struct drm_gpuvm *
a2xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev)
{
struct msm_mmu *mmu = a2xx_gpummu_new(&pdev->dev, gpu);
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", SZ_16M, 0xfff * SZ_64K, true);

3
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View File

@ -1786,7 +1786,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
return ERR_PTR(ret);
}
msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a5xx_fault_handler);
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
a5xx_fault_handler);
/* Set up the preemption specific bits and pieces for each ringbuffer */
a5xx_preempt_init(gpu);

6
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View File

@ -1259,6 +1259,8 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
{
struct msm_mmu *mmu = to_msm_vm(gmu->vm)->mmu;
msm_gem_kernel_put(gmu->hfi.obj, gmu->vm);
msm_gem_kernel_put(gmu->debug.obj, gmu->vm);
msm_gem_kernel_put(gmu->icache.obj, gmu->vm);
@ -1266,8 +1268,8 @@ static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
msm_gem_kernel_put(gmu->dummy.obj, gmu->vm);
msm_gem_kernel_put(gmu->log.obj, gmu->vm);
gmu->vm->mmu->funcs->detach(gmu->vm->mmu);
msm_gem_vm_put(gmu->vm);
mmu->funcs->detach(mmu);
drm_gpuvm_put(gmu->vm);
}
static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,

2
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
View File

@ -62,7 +62,7 @@ struct a6xx_gmu {
/* For serializing communication with the GMU: */
struct mutex lock;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
void __iomem *mmio;
void __iomem *rscc;

11
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -120,7 +120,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
if (ctx->seqno == ring->cur_ctx_seqno)
return;
if (msm_iommu_pagetable_params(ctx->vm->mmu, &ttbr, &asid))
if (msm_iommu_pagetable_params(to_msm_vm(ctx->vm)->mmu, &ttbr, &asid))
return;
if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) {
@ -2256,7 +2256,7 @@ static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
mutex_unlock(&a6xx_gpu->gmu.lock);
}
static struct msm_gem_vm *
static struct drm_gpuvm *
a6xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@ -2274,12 +2274,12 @@ a6xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev)
return adreno_iommu_create_vm(gpu, pdev, quirks);
}
static struct msm_gem_vm *
static struct drm_gpuvm *
a6xx_create_private_vm(struct msm_gpu *gpu)
{
struct msm_mmu *mmu;
mmu = msm_iommu_pagetable_create(gpu->vm->mmu);
mmu = msm_iommu_pagetable_create(to_msm_vm(gpu->vm)->mmu);
if (IS_ERR(mmu))
return ERR_CAST(mmu);
@ -2559,7 +2559,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a6xx_fault_handler);
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
a6xx_fault_handler);
a6xx_calc_ubwc_config(adreno_gpu);
/* Set up the preemption specific bits and pieces for each ringbuffer */

2
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
View File

@ -377,7 +377,7 @@ static int preempt_init_ring(struct a6xx_gpu *a6xx_gpu,
struct a7xx_cp_smmu_info *smmu_info_ptr = ptr;
msm_iommu_pagetable_params(gpu->vm->mmu, &ttbr, &asid);
msm_iommu_pagetable_params(to_msm_vm(gpu->vm)->mmu, &ttbr, &asid);
smmu_info_ptr->magic = GEN7_CP_SMMU_INFO_MAGIC;
smmu_info_ptr->ttbr0 = ttbr;

19
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -191,21 +191,21 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
}
struct msm_gem_vm *
struct drm_gpuvm *
adreno_create_vm(struct msm_gpu *gpu,
struct platform_device *pdev)
{
return adreno_iommu_create_vm(gpu, pdev, 0);
}
struct msm_gem_vm *
struct drm_gpuvm *
adreno_iommu_create_vm(struct msm_gpu *gpu,
struct platform_device *pdev,
unsigned long quirks)
{
struct iommu_domain_geometry *geometry;
struct msm_mmu *mmu;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
u64 start, size;
mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks);
@ -275,9 +275,11 @@ void adreno_check_and_reenable_stall(struct adreno_gpu *adreno_gpu)
if (!priv->stall_enabled &&
ktime_after(ktime_get(), priv->stall_reenable_time) &&
!READ_ONCE(gpu->crashstate)) {
struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
priv->stall_enabled = true;
gpu->vm->mmu->funcs->set_stall(gpu->vm->mmu, true);
mmu->funcs->set_stall(mmu, true);
}
spin_unlock_irqrestore(&priv->fault_stall_lock, flags);
}
@ -292,6 +294,7 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
u32 scratch[4])
{
struct msm_drm_private *priv = gpu->dev->dev_private;
struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
const char *type = "UNKNOWN";
bool do_devcoredump = info && (info->fsr & ARM_SMMU_FSR_SS) &&
!READ_ONCE(gpu->crashstate);
@ -305,7 +308,7 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
if (priv->stall_enabled) {
priv->stall_enabled = false;
gpu->vm->mmu->funcs->set_stall(gpu->vm->mmu, false);
mmu->funcs->set_stall(mmu, false);
}
priv->stall_reenable_time = ktime_add_ms(ktime_get(), 500);
@ -405,7 +408,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
return 0;
case MSM_PARAM_FAULTS:
if (ctx->vm)
*value = gpu->global_faults + ctx->vm->faults;
*value = gpu->global_faults + to_msm_vm(ctx->vm)->faults;
else
*value = gpu->global_faults;
return 0;
@ -415,12 +418,12 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
case MSM_PARAM_VA_START:
if (ctx->vm == gpu->vm)
return UERR(EINVAL, drm, "requires per-process pgtables");
*value = ctx->vm->base.mm_start;
*value = ctx->vm->mm_start;
return 0;
case MSM_PARAM_VA_SIZE:
if (ctx->vm == gpu->vm)
return UERR(EINVAL, drm, "requires per-process pgtables");
*value = ctx->vm->base.mm_range;
*value = ctx->vm->mm_range;
return 0;
case MSM_PARAM_HIGHEST_BANK_BIT:
*value = adreno_gpu->ubwc_config.highest_bank_bit;

4
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@ -622,11 +622,11 @@ void adreno_show_object(struct drm_printer *p, void **ptr, int len,
* Common helper function to initialize the default address space for arm-smmu
* attached targets
*/
struct msm_gem_vm *
struct drm_gpuvm *
adreno_create_vm(struct msm_gpu *gpu,
struct platform_device *pdev);
struct msm_gem_vm *
struct drm_gpuvm *
adreno_iommu_create_vm(struct msm_gpu *gpu,
struct platform_device *pdev,
unsigned long quirks);

6
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -1098,17 +1098,17 @@ static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
if (!dpu_kms->base.vm)
return;
mmu = dpu_kms->base.vm->mmu;
mmu = to_msm_vm(dpu_kms->base.vm)->mmu;
mmu->funcs->detach(mmu);
msm_gem_vm_put(dpu_kms->base.vm);
drm_gpuvm_put(dpu_kms->base.vm);
dpu_kms->base.vm = NULL;
}
static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
{
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
vm = msm_kms_init_vm(dpu_kms->dev);
if (IS_ERR(vm))

11
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
View File

@ -122,15 +122,16 @@ static void mdp4_destroy(struct msm_kms *kms)
{
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
struct device *dev = mdp4_kms->dev->dev;
struct msm_gem_vm *vm = kms->vm;
if (mdp4_kms->blank_cursor_iova)
msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->vm);
drm_gem_object_put(mdp4_kms->blank_cursor_bo);
if (vm) {
vm->mmu->funcs->detach(vm->mmu);
msm_gem_vm_put(vm);
if (kms->vm) {
struct msm_mmu *mmu = to_msm_vm(kms->vm)->mmu;
mmu->funcs->detach(mmu);
drm_gpuvm_put(kms->vm);
}
if (mdp4_kms->rpm_enabled)
@ -398,7 +399,7 @@ static int mdp4_kms_init(struct drm_device *dev)
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms));
struct msm_kms *kms = NULL;
struct msm_mmu *mmu;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
int ret;
u32 major, minor;
unsigned long max_clk;

11
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
View File

@ -198,11 +198,12 @@ static void mdp5_destroy(struct mdp5_kms *mdp5_kms);
static void mdp5_kms_destroy(struct msm_kms *kms)
{
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct msm_gem_vm *vm = kms->vm;
if (vm) {
vm->mmu->funcs->detach(vm->mmu);
msm_gem_vm_put(vm);
if (kms->vm) {
struct msm_mmu *mmu = to_msm_vm(kms->vm)->mmu;
mmu->funcs->detach(mmu);
drm_gpuvm_put(kms->vm);
}
mdp_kms_destroy(&mdp5_kms->base);
@ -500,7 +501,7 @@ static int mdp5_kms_init(struct drm_device *dev)
struct mdp5_kms *mdp5_kms;
struct mdp5_cfg *config;
struct msm_kms *kms = priv->kms;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
int i, ret;
ret = mdp5_init(to_platform_device(dev->dev), dev);

6
drivers/gpu/drm/msm/dsi/dsi_host.c
View File

@ -152,7 +152,7 @@ struct msm_dsi_host {
/* DSI 6G TX buffer*/
struct drm_gem_object *tx_gem_obj;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
/* DSI v2 TX buffer */
void *tx_buf;
@ -1207,7 +1207,7 @@ int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
uint64_t iova;
u8 *data;
msm_host->vm = msm_gem_vm_get(priv->kms->vm);
msm_host->vm = drm_gpuvm_get(priv->kms->vm);
data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
msm_host->vm,
@ -1255,7 +1255,7 @@ void msm_dsi_tx_buf_free(struct mipi_dsi_host *host)
if (msm_host->tx_gem_obj) {
msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm);
msm_gem_vm_put(msm_host->vm);
drm_gpuvm_put(msm_host->vm);
msm_host->tx_gem_obj = NULL;
msm_host->vm = NULL;
}

4
drivers/gpu/drm/msm/msm_drv.h
View File

@ -48,8 +48,6 @@ struct msm_rd_state;
struct msm_perf_state;
struct msm_gem_submit;
struct msm_fence_context;
struct msm_gem_vm;
struct msm_gem_vma;
struct msm_disp_state;
#define MAX_CRTCS 8
@ -253,7 +251,7 @@ void msm_crtc_disable_vblank(struct drm_crtc *crtc);
int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
struct msm_gem_vm *msm_kms_init_vm(struct drm_device *dev);
struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev);
bool msm_use_mmu(struct drm_device *dev);
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,

4
drivers/gpu/drm/msm/msm_fb.c
View File

@ -78,7 +78,7 @@ void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m)
int msm_framebuffer_prepare(struct drm_framebuffer *fb, bool needs_dirtyfb)
{
struct msm_drm_private *priv = fb->dev->dev_private;
struct msm_gem_vm *vm = priv->kms->vm;
struct drm_gpuvm *vm = priv->kms->vm;
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
int ret, i, n = fb->format->num_planes;
@ -102,7 +102,7 @@ int msm_framebuffer_prepare(struct drm_framebuffer *fb, bool needs_dirtyfb)
void msm_framebuffer_cleanup(struct drm_framebuffer *fb, bool needed_dirtyfb)
{
struct msm_drm_private *priv = fb->dev->dev_private;
struct msm_gem_vm *vm = priv->kms->vm;
struct drm_gpuvm *vm = priv->kms->vm;
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
int i, n = fb->format->num_planes;

94
drivers/gpu/drm/msm/msm_gem.c
View File

@ -45,20 +45,20 @@ static int msm_gem_open(struct drm_gem_object *obj, struct drm_file *file)
static void put_iova_spaces(struct drm_gem_object *obj, struct drm_gpuvm *vm, bool close);
static void detach_vm(struct drm_gem_object *obj, struct msm_gem_vm *vm)
static void detach_vm(struct drm_gem_object *obj, struct drm_gpuvm *vm)
{
msm_gem_assert_locked(obj);
drm_gpuvm_resv_assert_held(&vm->base);
drm_gpuvm_resv_assert_held(vm);
struct drm_gpuvm_bo *vm_bo = drm_gpuvm_bo_find(&vm->base, obj);
struct drm_gpuvm_bo *vm_bo = drm_gpuvm_bo_find(vm, obj);
if (vm_bo) {
struct drm_gpuva *vma;
drm_gpuvm_bo_for_each_va (vma, vm_bo) {
if (vma->vm != &vm->base)
if (vma->vm != vm)
continue;
msm_gem_vma_purge(to_msm_vma(vma));
msm_gem_vma_close(to_msm_vma(vma));
msm_gem_vma_purge(vma);
msm_gem_vma_close(vma);
break;
}
@ -89,7 +89,7 @@ static void msm_gem_close(struct drm_gem_object *obj, struct drm_file *file)
msecs_to_jiffies(1000));
msm_gem_lock_vm_and_obj(&exec, obj, ctx->vm);
put_iova_spaces(obj, &ctx->vm->base, true);
put_iova_spaces(obj, ctx->vm, true);
detach_vm(obj, ctx->vm);
drm_exec_fini(&exec); /* drop locks */
}
@ -386,8 +386,8 @@ uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj)
return offset;
}
static struct msm_gem_vma *lookup_vma(struct drm_gem_object *obj,
struct msm_gem_vm *vm)
static struct drm_gpuva *lookup_vma(struct drm_gem_object *obj,
struct drm_gpuvm *vm)
{
struct drm_gpuvm_bo *vm_bo;
@ -397,13 +397,13 @@ static struct msm_gem_vma *lookup_vma(struct drm_gem_object *obj,
struct drm_gpuva *vma;
drm_gpuvm_bo_for_each_va (vma, vm_bo) {
if (vma->vm == &vm->base) {
if (vma->vm == vm) {
/* lookup_vma() should only be used in paths
* with at most one vma per vm
*/
GEM_WARN_ON(!list_is_singular(&vm_bo->list.gpuva));
return to_msm_vma(vma);
return vma;
}
}
}
@ -433,22 +433,20 @@ put_iova_spaces(struct drm_gem_object *obj, struct drm_gpuvm *vm, bool close)
drm_gpuvm_bo_get(vm_bo);
drm_gpuvm_bo_for_each_va_safe (vma, vmatmp, vm_bo) {
struct msm_gem_vma *msm_vma = to_msm_vma(vma);
msm_gem_vma_purge(msm_vma);
msm_gem_vma_purge(vma);
if (close)
msm_gem_vma_close(msm_vma);
msm_gem_vma_close(vma);
}
drm_gpuvm_bo_put(vm_bo);
}
}
static struct msm_gem_vma *get_vma_locked(struct drm_gem_object *obj,
struct msm_gem_vm *vm,
u64 range_start, u64 range_end)
static struct drm_gpuva *get_vma_locked(struct drm_gem_object *obj,
struct drm_gpuvm *vm, u64 range_start,
u64 range_end)
{
struct msm_gem_vma *vma;
struct drm_gpuva *vma;
msm_gem_assert_locked(obj);
@ -457,14 +455,14 @@ static struct msm_gem_vma *get_vma_locked(struct drm_gem_object *obj,
if (!vma) {
vma = msm_gem_vma_new(vm, obj, range_start, range_end);
} else {
GEM_WARN_ON(vma->base.va.addr < range_start);
GEM_WARN_ON((vma->base.va.addr + obj->size) > range_end);
GEM_WARN_ON(vma->va.addr < range_start);
GEM_WARN_ON((vma->va.addr + obj->size) > range_end);
}
return vma;
}
int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma)
int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct drm_gpuva *vma)
{
struct msm_gem_object *msm_obj = to_msm_bo(obj);
struct page **pages;
@ -517,17 +515,17 @@ void msm_gem_unpin_active(struct drm_gem_object *obj)
update_lru_active(obj);
}
struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
struct msm_gem_vm *vm)
struct drm_gpuva *msm_gem_get_vma_locked(struct drm_gem_object *obj,
struct drm_gpuvm *vm)
{
return get_vma_locked(obj, vm, 0, U64_MAX);
}
static int get_and_pin_iova_range_locked(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova,
u64 range_start, u64 range_end)
struct drm_gpuvm *vm, uint64_t *iova,
u64 range_start, u64 range_end)
{
struct msm_gem_vma *vma;
struct drm_gpuva *vma;
int ret;
msm_gem_assert_locked(obj);
@ -538,7 +536,7 @@ static int get_and_pin_iova_range_locked(struct drm_gem_object *obj,
ret = msm_gem_pin_vma_locked(obj, vma);
if (!ret) {
*iova = vma->base.va.addr;
*iova = vma->va.addr;
pin_obj_locked(obj);
}
@ -550,8 +548,8 @@ static int get_and_pin_iova_range_locked(struct drm_gem_object *obj,
* limits iova to specified range (in pages)
*/
int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova,
u64 range_start, u64 range_end)
struct drm_gpuvm *vm, uint64_t *iova,
u64 range_start, u64 range_end)
{
struct drm_exec exec;
int ret;
@ -564,8 +562,8 @@ int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
}
/* get iova and pin it. Should have a matching put */
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova)
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm,
uint64_t *iova)
{
return msm_gem_get_and_pin_iova_range(obj, vm, iova, 0, U64_MAX);
}
@ -574,10 +572,10 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
* Get an iova but don't pin it. Doesn't need a put because iovas are currently
* valid for the life of the object
*/
int msm_gem_get_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova)
int msm_gem_get_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm,
uint64_t *iova)
{
struct msm_gem_vma *vma;
struct drm_gpuva *vma;
struct drm_exec exec;
int ret = 0;
@ -586,7 +584,7 @@ int msm_gem_get_iova(struct drm_gem_object *obj,
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
} else {
*iova = vma->base.va.addr;
*iova = vma->va.addr;
}
drm_exec_fini(&exec); /* drop locks */
@ -594,9 +592,9 @@ int msm_gem_get_iova(struct drm_gem_object *obj,
}
static int clear_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm)
struct drm_gpuvm *vm)
{
struct msm_gem_vma *vma = lookup_vma(obj, vm);
struct drm_gpuva *vma = lookup_vma(obj, vm);
if (!vma)
return 0;
@ -615,7 +613,7 @@ static int clear_iova(struct drm_gem_object *obj,
* Setting an iova of zero will clear the vma.
*/
int msm_gem_set_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t iova)
struct drm_gpuvm *vm, uint64_t iova)
{
struct drm_exec exec;
int ret = 0;
@ -624,11 +622,11 @@ int msm_gem_set_iova(struct drm_gem_object *obj,
if (!iova) {
ret = clear_iova(obj, vm);
} else {
struct msm_gem_vma *vma;
struct drm_gpuva *vma;
vma = get_vma_locked(obj, vm, iova, iova + obj->size);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
} else if (GEM_WARN_ON(vma->base.va.addr != iova)) {
} else if (GEM_WARN_ON(vma->va.addr != iova)) {
clear_iova(obj, vm);
ret = -EBUSY;
}
@ -643,10 +641,9 @@ int msm_gem_set_iova(struct drm_gem_object *obj,
* purged until something else (shrinker, mm_notifier, destroy, etc) decides
* to get rid of it
*/
void msm_gem_unpin_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm)
void msm_gem_unpin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm)
{
struct msm_gem_vma *vma;
struct drm_gpuva *vma;
struct drm_exec exec;
msm_gem_lock_vm_and_obj(&exec, obj, vm);
@ -1276,9 +1273,9 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev,
return ERR_PTR(ret);
}
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
uint32_t flags, struct msm_gem_vm *vm,
struct drm_gem_object **bo, uint64_t *iova)
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t flags,
struct drm_gpuvm *vm, struct drm_gem_object **bo,
uint64_t *iova)
{
void *vaddr;
struct drm_gem_object *obj = msm_gem_new(dev, size, flags);
@ -1311,8 +1308,7 @@ void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
}
void msm_gem_kernel_put(struct drm_gem_object *bo,
struct msm_gem_vm *vm)
void msm_gem_kernel_put(struct drm_gem_object *bo, struct drm_gpuvm *vm)
{
if (IS_ERR_OR_NULL(bo))
return;

59
drivers/gpu/drm/msm/msm_gem.h
View File

@ -79,12 +79,7 @@ struct msm_gem_vm {
};
#define to_msm_vm(x) container_of(x, struct msm_gem_vm, base)
struct msm_gem_vm *
msm_gem_vm_get(struct msm_gem_vm *vm);
void msm_gem_vm_put(struct msm_gem_vm *vm);
struct msm_gem_vm *
struct drm_gpuvm *
msm_gem_vm_create(struct drm_device *drm, struct msm_mmu *mmu, const char *name,
u64 va_start, u64 va_size, bool managed);
@ -113,12 +108,12 @@ struct msm_gem_vma {
};
#define to_msm_vma(x) container_of(x, struct msm_gem_vma, base)
struct msm_gem_vma *
msm_gem_vma_new(struct msm_gem_vm *vm, struct drm_gem_object *obj,
struct drm_gpuva *
msm_gem_vma_new(struct drm_gpuvm *vm, struct drm_gem_object *obj,
u64 range_start, u64 range_end);
void msm_gem_vma_purge(struct msm_gem_vma *vma);
int msm_gem_vma_map(struct msm_gem_vma *vma, int prot, struct sg_table *sgt, int size);
void msm_gem_vma_close(struct msm_gem_vma *vma);
void msm_gem_vma_purge(struct drm_gpuva *vma);
int msm_gem_vma_map(struct drm_gpuva *vma, int prot, struct sg_table *sgt, int size);
void msm_gem_vma_close(struct drm_gpuva *vma);
struct msm_gem_object {
struct drm_gem_object base;
@ -163,22 +158,21 @@ struct msm_gem_object {
#define to_msm_bo(x) container_of(x, struct msm_gem_object, base)
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma);
int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct drm_gpuva *vma);
void msm_gem_unpin_locked(struct drm_gem_object *obj);
void msm_gem_unpin_active(struct drm_gem_object *obj);
struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
struct msm_gem_vm *vm);
int msm_gem_get_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova);
int msm_gem_set_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t iova);
struct drm_gpuva *msm_gem_get_vma_locked(struct drm_gem_object *obj,
struct drm_gpuvm *vm);
int msm_gem_get_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm,
uint64_t *iova);
int msm_gem_set_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm,
uint64_t iova);
int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova,
u64 range_start, u64 range_end);
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm, uint64_t *iova);
void msm_gem_unpin_iova(struct drm_gem_object *obj,
struct msm_gem_vm *vm);
struct drm_gpuvm *vm, uint64_t *iova,
u64 range_start, u64 range_end);
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm,
uint64_t *iova);
void msm_gem_unpin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm);
void msm_gem_pin_obj_locked(struct drm_gem_object *obj);
struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj);
void msm_gem_unpin_pages_locked(struct drm_gem_object *obj);
@ -199,11 +193,10 @@ int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
uint32_t size, uint32_t flags, uint32_t *handle, char *name);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
uint32_t size, uint32_t flags);
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
uint32_t flags, struct msm_gem_vm *vm,
struct drm_gem_object **bo, uint64_t *iova);
void msm_gem_kernel_put(struct drm_gem_object *bo,
struct msm_gem_vm *vm);
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, uint32_t flags,
struct drm_gpuvm *vm, struct drm_gem_object **bo,
uint64_t *iova);
void msm_gem_kernel_put(struct drm_gem_object *bo, struct drm_gpuvm *vm);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
struct dma_buf *dmabuf, struct sg_table *sgt);
__printf(2, 3)
@ -254,14 +247,14 @@ msm_gem_unlock(struct drm_gem_object *obj)
static inline int
msm_gem_lock_vm_and_obj(struct drm_exec *exec,
struct drm_gem_object *obj,
struct msm_gem_vm *vm)
struct drm_gpuvm *vm)
{
int ret = 0;
drm_exec_init(exec, 0, 2);
drm_exec_until_all_locked (exec) {
ret = drm_exec_lock_obj(exec, drm_gpuvm_resv_obj(&vm->base));
if (!ret && (obj->resv != drm_gpuvm_resv(&vm->base)))
ret = drm_exec_lock_obj(exec, drm_gpuvm_resv_obj(vm));
if (!ret && (obj->resv != drm_gpuvm_resv(vm)))
ret = drm_exec_lock_obj(exec, obj);
drm_exec_retry_on_contention(exec);
if (GEM_WARN_ON(ret))
@ -328,7 +321,7 @@ struct msm_gem_submit {
struct kref ref;
struct drm_device *dev;
struct msm_gpu *gpu;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
struct list_head node; /* node in ring submit list */
struct drm_exec exec;
uint32_t seqno; /* Sequence number of the submit on the ring */

8
drivers/gpu/drm/msm/msm_gem_submit.c
View File

@ -264,7 +264,7 @@ static int submit_lock_objects(struct msm_gem_submit *submit)
drm_exec_until_all_locked (&submit->exec) {
ret = drm_exec_lock_obj(&submit->exec,
drm_gpuvm_resv_obj(&submit->vm->base));
drm_gpuvm_resv_obj(submit->vm));
drm_exec_retry_on_contention(&submit->exec);
if (ret)
goto error;
@ -315,7 +315,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
for (i = 0; i < submit->nr_bos; i++) {
struct drm_gem_object *obj = submit->bos[i].obj;
struct msm_gem_vma *vma;
struct drm_gpuva *vma;
/* if locking succeeded, pin bo: */
vma = msm_gem_get_vma_locked(obj, submit->vm);
@ -328,8 +328,8 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
if (ret)
break;
submit->bos[i].vm_bo = drm_gpuvm_bo_get(vma->base.vm_bo);
submit->bos[i].iova = vma->base.va.addr;
submit->bos[i].vm_bo = drm_gpuvm_bo_get(vma->vm_bo);
submit->bos[i].iova = vma->va.addr;
}
/*

70
drivers/gpu/drm/msm/msm_gem_vma.c
View File

@ -20,52 +20,38 @@ msm_gem_vm_free(struct drm_gpuvm *gpuvm)
kfree(vm);
}
void msm_gem_vm_put(struct msm_gem_vm *vm)
{
if (vm)
drm_gpuvm_put(&vm->base);
}
struct msm_gem_vm *
msm_gem_vm_get(struct msm_gem_vm *vm)
{
if (!IS_ERR_OR_NULL(vm))
drm_gpuvm_get(&vm->base);
return vm;
}
/* Actually unmap memory for the vma */
void msm_gem_vma_purge(struct msm_gem_vma *vma)
void msm_gem_vma_purge(struct drm_gpuva *vma)
{
struct msm_gem_vm *vm = to_msm_vm(vma->base.vm);
unsigned size = vma->base.va.range;
struct msm_gem_vma *msm_vma = to_msm_vma(vma);
struct msm_gem_vm *vm = to_msm_vm(vma->vm);
unsigned size = vma->va.range;
/* Don't do anything if the memory isn't mapped */
if (!vma->mapped)
if (!msm_vma->mapped)
return;
vm->mmu->funcs->unmap(vm->mmu, vma->base.va.addr, size);
vm->mmu->funcs->unmap(vm->mmu, vma->va.addr, size);
vma->mapped = false;
msm_vma->mapped = false;
}
/* Map and pin vma: */
int
msm_gem_vma_map(struct msm_gem_vma *vma, int prot,
msm_gem_vma_map(struct drm_gpuva *vma, int prot,
struct sg_table *sgt, int size)
{
struct msm_gem_vm *vm = to_msm_vm(vma->base.vm);
struct msm_gem_vma *msm_vma = to_msm_vma(vma);
struct msm_gem_vm *vm = to_msm_vm(vma->vm);
int ret;
if (GEM_WARN_ON(!vma->base.va.addr))
if (GEM_WARN_ON(!vma->va.addr))
return -EINVAL;
if (vma->mapped)
if (msm_vma->mapped)
return 0;
vma->mapped = true;
msm_vma->mapped = true;
/*
* NOTE: iommu/io-pgtable can allocate pages, so we cannot hold
@ -76,38 +62,40 @@ msm_gem_vma_map(struct msm_gem_vma *vma, int prot,
* Revisit this if we can come up with a scheme to pre-alloc pages
* for the pgtable in map/unmap ops.
*/
ret = vm->mmu->funcs->map(vm->mmu, vma->base.va.addr, sgt, size, prot);
ret = vm->mmu->funcs->map(vm->mmu, vma->va.addr, sgt, size, prot);
if (ret) {
vma->mapped = false;
msm_vma->mapped = false;
}
return ret;
}
/* Close an iova. Warn if it is still in use */
void msm_gem_vma_close(struct msm_gem_vma *vma)
void msm_gem_vma_close(struct drm_gpuva *vma)
{
struct msm_gem_vm *vm = to_msm_vm(vma->base.vm);
struct msm_gem_vm *vm = to_msm_vm(vma->vm);
struct msm_gem_vma *msm_vma = to_msm_vma(vma);
GEM_WARN_ON(vma->mapped);
GEM_WARN_ON(msm_vma->mapped);
drm_gpuvm_resv_assert_held(&vm->base);
if (vma->base.va.addr)
drm_mm_remove_node(&vma->node);
if (vma->va.addr && vm->managed)
drm_mm_remove_node(&msm_vma->node);
drm_gpuva_remove(&vma->base);
drm_gpuva_unlink(&vma->base);
drm_gpuva_remove(vma);
drm_gpuva_unlink(vma);
kfree(vma);
}
/* Create a new vma and allocate an iova for it */
struct msm_gem_vma *
msm_gem_vma_new(struct msm_gem_vm *vm, struct drm_gem_object *obj,
struct drm_gpuva *
msm_gem_vma_new(struct drm_gpuvm *gpuvm, struct drm_gem_object *obj,
u64 range_start, u64 range_end)
{
struct msm_gem_vm *vm = to_msm_vm(gpuvm);
struct drm_gpuvm_bo *vm_bo;
struct msm_gem_vma *vma;
int ret;
@ -149,7 +137,7 @@ msm_gem_vma_new(struct msm_gem_vm *vm, struct drm_gem_object *obj,
drm_gpuva_link(&vma->base, vm_bo);
GEM_WARN_ON(drm_gpuvm_bo_put(vm_bo));
return vma;
return &vma->base;
err_va_remove:
drm_gpuva_remove(&vma->base);
@ -179,7 +167,7 @@ static const struct drm_gpuvm_ops msm_gpuvm_ops = {
* handles virtual address allocation, and both async and sync operations
* are supported.
*/
struct msm_gem_vm *
struct drm_gpuvm *
msm_gem_vm_create(struct drm_device *drm, struct msm_mmu *mmu, const char *name,
u64 va_start, u64 va_size, bool managed)
{
@ -215,7 +203,7 @@ msm_gem_vm_create(struct drm_device *drm, struct msm_mmu *mmu, const char *name,
drm_mm_init(&vm->mm, va_start, va_size);
return vm;
return &vm->base;
err_free_vm:
kfree(vm);

18
drivers/gpu/drm/msm/msm_gpu.c
View File

@ -285,7 +285,7 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
if (state->fault_info.ttbr0) {
struct msm_gpu_fault_info *info = &state->fault_info;
struct msm_mmu *mmu = submit->vm->mmu;
struct msm_mmu *mmu = to_msm_vm(submit->vm)->mmu;
msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0,
&info->asid);
@ -390,7 +390,7 @@ static void recover_worker(struct kthread_work *work)
/* Increment the fault counts */
submit->queue->faults++;
if (submit->vm)
submit->vm->faults++;
to_msm_vm(submit->vm)->faults++;
get_comm_cmdline(submit, &comm, &cmd);
@ -828,10 +828,11 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
}
/* Return a new address space for a msm_drm_private instance */
struct msm_gem_vm *
struct drm_gpuvm *
msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task)
{
struct msm_gem_vm *vm = NULL;
struct drm_gpuvm *vm = NULL;
if (!gpu)
return NULL;
@ -842,11 +843,11 @@ msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task)
if (gpu->funcs->create_private_vm) {
vm = gpu->funcs->create_private_vm(gpu);
if (!IS_ERR(vm))
vm->pid = get_pid(task_pid(task));
to_msm_vm(vm)->pid = get_pid(task_pid(task));
}
if (IS_ERR_OR_NULL(vm))
vm = msm_gem_vm_get(gpu->vm);
vm = drm_gpuvm_get(gpu->vm);
return vm;
}
@ -1014,8 +1015,9 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
if (!IS_ERR_OR_NULL(gpu->vm)) {
gpu->vm->mmu->funcs->detach(gpu->vm->mmu);
msm_gem_vm_put(gpu->vm);
struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
mmu->funcs->detach(mmu);
drm_gpuvm_put(gpu->vm);
}
if (gpu->worker) {

10
drivers/gpu/drm/msm/msm_gpu.h
View File

@ -78,8 +78,8 @@ struct msm_gpu_funcs {
/* note: gpu_set_freq() can assume that we have been pm_resumed */
void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
bool suspended);
struct msm_gem_vm *(*create_vm)(struct msm_gpu *gpu, struct platform_device *pdev);
struct msm_gem_vm *(*create_private_vm)(struct msm_gpu *gpu);
struct drm_gpuvm *(*create_vm)(struct msm_gpu *gpu, struct platform_device *pdev);
struct drm_gpuvm *(*create_private_vm)(struct msm_gpu *gpu);
uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
/**
@ -234,7 +234,7 @@ struct msm_gpu {
void __iomem *mmio;
int irq;
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
/* Power Control: */
struct regulator *gpu_reg, *gpu_cx;
@ -357,7 +357,7 @@ struct msm_context {
int queueid;
/** @vm: the per-process GPU address-space */
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
/** @kref: the reference count */
struct kref ref;
@ -667,7 +667,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
const char *name, struct msm_gpu_config *config);
struct msm_gem_vm *
struct drm_gpuvm *
msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task);
void msm_gpu_cleanup(struct msm_gpu *gpu);

6
drivers/gpu/drm/msm/msm_kms.c
View File

@ -176,9 +176,9 @@ static int msm_kms_fault_handler(void *arg, unsigned long iova, int flags, void
return -ENOSYS;
}
struct msm_gem_vm *msm_kms_init_vm(struct drm_device *dev)
struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev)
{
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
struct msm_mmu *mmu;
struct device *mdp_dev = dev->dev;
struct device *mdss_dev = mdp_dev->parent;
@ -212,7 +212,7 @@ struct msm_gem_vm *msm_kms_init_vm(struct drm_device *dev)
return vm;
}
msm_mmu_set_fault_handler(vm->mmu, kms, msm_kms_fault_handler);
msm_mmu_set_fault_handler(to_msm_vm(vm)->mmu, kms, msm_kms_fault_handler);
return vm;
}

2
drivers/gpu/drm/msm/msm_kms.h
View File

@ -139,7 +139,7 @@ struct msm_kms {
atomic_t fault_snapshot_capture;
/* mapper-id used to request GEM buffer mapped for scanout: */
struct msm_gem_vm *vm;
struct drm_gpuvm *vm;
/* disp snapshot support */
struct kthread_worker *dump_worker;

2
drivers/gpu/drm/msm/msm_submitqueue.c
View File

@ -59,7 +59,7 @@ void __msm_context_destroy(struct kref *kref)
kfree(ctx->entities[i]);
}
msm_gem_vm_put(ctx->vm);
drm_gpuvm_put(ctx->vm);
kfree(ctx->comm);
kfree(ctx->cmdline);
kfree(ctx);