dt-bindings: riscv: Add Zic64b extension description

Zic64b mandates that cache blocks are 64 bytes in size and naturally
aligned in the address space. It is a mandatory extension of both the
RVA22 (U64/S64) and RVA23 (U64/S64) profiles, ratified with RISC-V
Profiles Version 1.0.

Document it so it can be described in the riscv,isa-extensions property,
alongside the related Zicbom/Zicbop/Zicboz cache-block extensions. Since
Zic64b fixes the cache block size at 64 bytes, also add a schema check
requiring any present cbom/cbop/cboz block size to be 64. The check
matches only nodes that use riscv,isa-extensions, so nodes carrying
just the deprecated riscv,isa string are not affected.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-3-5f14bc5c23d3@oss.qualcomm.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Guodong Xu 2026-09-20 03:18:23 -04:00 committed by Paul Walmsley
parent 40623184c6
commit 3776fb1a1b

View File

@ -537,6 +537,12 @@ properties:
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
- const: zic64b
description:
The standard Zic64b extension for 64-byte naturally aligned cache
blocks, as ratified in RISC-V Profiles Version 1.0, with commit
b1d806605f87 ("Updated to ratified state.")
- const: zicbom
description:
The standard Zicbom extension for base cache management operations as
@ -1211,6 +1217,22 @@ allOf:
not:
contains:
const: zilsd
# Zic64b mandates 64-byte naturally aligned cache blocks
- if:
properties:
riscv,isa-extensions:
contains:
const: zic64b
required:
- riscv,isa-extensions
then:
properties:
riscv,cbom-block-size:
const: 64
riscv,cbop-block-size:
const: 64
riscv,cboz-block-size:
const: 64
# All three Zicbo* extensions require their block size property as there's no
# default.
- if: