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drm/vc4: hdmi: Add pixel BVB clock control
The BCM2711 has another clock that needs to be ramped up depending on the pixel rate: the pixel BVB clock. Add the code to adjust that clock when changing the mode. [Maxime: Changed the commit log, used clk_set_min_rate] Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20200901040759.29992-3-hoegeun.kwon@samsung.com Link: https://patchwork.freedesktop.org/patch/msgid/d757ddd6549da140f178563e5fd2bf1d129913fd.1599120059.git-series.maxime@cerno.tech
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@ -54,6 +54,7 @@
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#include "vc4_regs.h"
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#define CEC_CLOCK_FREQ 40000
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#define VC4_HSM_MID_CLOCK 149985000
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static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
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{
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@ -344,6 +345,7 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
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HDMI_WRITE(HDMI_VID_CTL,
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HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
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clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
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clk_disable_unprepare(vc4_hdmi->hsm_clock);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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@ -516,6 +518,27 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
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return;
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}
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/*
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* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
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* at 300MHz.
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*/
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ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
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(hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
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if (ret) {
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DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
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clk_disable_unprepare(vc4_hdmi->hsm_clock);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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return;
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}
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ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
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if (ret) {
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DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
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clk_disable_unprepare(vc4_hdmi->hsm_clock);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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return;
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}
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if (vc4_hdmi->variant->reset)
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vc4_hdmi->variant->reset(vc4_hdmi);
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@ -119,6 +119,7 @@ struct vc4_hdmi {
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struct clk *pixel_clock;
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struct clk *hsm_clock;
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struct clk *audio_clock;
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struct clk *pixel_bvb_clock;
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struct debugfs_regset32 hdmi_regset;
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struct debugfs_regset32 hd_regset;
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