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arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO

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This patch enables the PCIe2 on the CM4IO board when paired with
a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
enabled in this case to make the PHY work for this.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Nicolas Frattaroli 2022-11-12 17:04:01 +01:00 committed by Heiko Stuebner
parent 70b620c4ba
commit 3736aa7ecc
2 changed files with 26 additions and 0 deletions
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11
arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
View File

@ -30,6 +30,12 @@ vcc_5v: vcc-5v-regulator {
};
};
/* phy for pcie */
&combphy2 {
phy-supply = <&vcc3v3_sys>;
status = "okay";
};
&gmac1 {
status = "okay";
};
@ -105,6 +111,11 @@ &led_work {
status = "okay";
};
&pcie2x1 {
vpcie3v3-supply = <&vcc_3v3>;
status = "okay";
};
&rgmii_phy1 {
status = "okay";
};

15
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
View File

@ -487,6 +487,12 @@ rgmii_phy1: ethernet-phy@0 {
};
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_h>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
@ -512,6 +518,15 @@ diy_led_enable_h: diy-led-enable-h {
};
};
pcie {
pcie_clkreq_h: pcie-clkreq-h {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_reset_h: pcie-reset-h {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;