drm/i915/cx0: Fix port to PLL ID mapping on BMG

The intel_port_to_tc() call in mtl_port_to_pll_id() assumed that all
TypeC DDI ports are connected to a TypeC PHY. This is not true on BMG
where all the ports - including the PORT_TC1..4 TypeC DDI ports - are
connected to a non-TypeC PHY. For these ports intel_port_to_tc()
returns TC_PORT_NONE, which results in an incorrect port -> PLL ID
mapping. Fix this up by using the expected PORT_TC1..4 port ->
TC_PORT_1..4 tc_port mapping on BMG as well.

Fixes: ca1eda5cd4 ("drm/i915/cx0: Add MTL+ .get_dplls hook")
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-1-imre.deak@intel.com

drivers/gpu/drm/i915/display/intel_ddi.c

@@ -4294,9 +4294,10 @@ static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
 }
 
 /*
- * Get the configuration for either a port using a C10 PHY PLL, or in the case of
- * the PTL port B eDP on TypeC PHY case the configuration of a port using a C20
- * PHY PLL.
+ * Get the configuration for either a port using a C10 PHY PLL, or a port using a
+ * C20 PHY PLL in the cases of:
+ * - BMG port A/B
+ * - PTL port B eDP over TypeC PHY
  */
 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
 					     struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

@@ -206,7 +206,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
 {
 	if (port >= PORT_TC1)
-		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
+		return icl_tc_port_to_pll_id(port - PORT_TC1 + TC_PORT_1);
 
 	switch (port) {
 	case PORT_A:
@@ -3507,9 +3507,10 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 }
 
 /*
- * Get the PLL for either a port using a C10 PHY PLL, or in the
- * PTL port B eDP over TypeC PHY case, the PLL for a port using
- * a C20 PHY PLL.
+ * Get the PLL for either a port using a C10 PHY PLL, or for a port using a
+ * C20 PHY PLL in the cases of:
+ * - BMG port A/B
+ * - PTL port B eDP over TypeC PHY
  */
 static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc,