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video: rockchip: hdmi: 3368: enable detect phy pll lock status
Phy PLL may be unlock under electro-static test. The higher the electro-static voltage, the more likely the PLL will be lost. If PLL is unlock and irq is triggered, we will reset registers to make it lock on correct frequency. Change-Id: I86eaa660e837e8c2e59c8e39e3ce083bb89c1bac Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
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@ -317,6 +317,7 @@ static const struct phy_mpll_config_tab *get_phy_mpll_tab(
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static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
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{
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hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
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hdmi_msk_reg(hdmi_dev, PHY_CONF0,
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m_PDDQ_SIG | m_TXPWRON_SIG |
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m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
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@ -409,6 +410,7 @@ static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
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hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
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m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
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hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
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/* power off PHY */
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/* hdmi_writel(hdmi_dev, PHY_CONF0, 0x1e); */
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hdmi_msk_reg(hdmi_dev, PHY_CONF0,
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@ -514,7 +516,7 @@ static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
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(stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
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return -1;
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}
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hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
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return 0;
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}
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@ -1330,6 +1332,8 @@ static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
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if (!hdmi->uboot)
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rockchip_hdmiv2_config_phy(hdmi_dev);
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else
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hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
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return 0;
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}
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@ -1702,7 +1706,7 @@ void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
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hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
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hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
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hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
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hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfe);
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hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfc);
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hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
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hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
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hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
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@ -1744,6 +1748,11 @@ irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
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hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
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if (phy_int0 || phy_int) {
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if ((phy_int0 & m_PHY_LOCK) &&
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(phy_pol & m_PHY_LOCK) == 0) {
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pr_info("hdmi phy pll unlock\n");
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hdmi_submit_work(hdmi, HDMI_SET_VIDEO, 0, 0);
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}
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phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
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hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
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hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
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