github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-26 16:12:59 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Allwinner Device Tree changes for 6.14

Browse Source 
- Add support for DMA engine and audio codec on F1C100s
   and enable audio codec on Lichee Pi Nano
 - Add syscon and SRAM nodes for A100
 - Enable CPU DVFS for Tanix TX1
 - Explicitly configure TCON0 pixel clock parent according to display
   output used
 
 This includes one commit shared with the clock tree
 
     dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
 
 which adds the macros for the TCON0 pixel clock parents.
 -----BEGIN PGP SIGNATURE-----
 
 iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmd+iXwOHHdlbnNAY3Np
 ZS5vcmcACgkQOJpUIZwPJDBXjRAAtDe3dNrPw9vcsv1d0xVp2J3Q4gOGLhf/BzN+
 +1Bg1ETngDwkHF11KAD38t+3z/Kccg63tsy8F8GBzE9MxhDUka3IdIV9WZkeRcn0
 Cb97gtPAc3yawgGtOwNbzf/5YFU26z89X3m2yLl2JcXXp2KN+aHt4yccCNi1s+79
 lJBKzDNVlEVxsqRYAJtC13FLNfoG/oGKjAG7+qJu79WjjlXJu55eEGfLOHQFhpVX
 rUauQkY2uOxRJ8AqA/YjqY3zSSQW0N1dp6KGhxy2IjXcE9sBOG3G6CsRTfzXMYXb
 b78viKGSz/vahUs82Tnb9OI6kAOMS06rRrI6wmZzsb9hopC2LUKX2u9oJwUN31SI
 Oz5tCgGgt8Do63KW3Ds9BORvqg6MymMmjf8KCHieOm3WXuKElHY4lY5X2y/FK1jH
 JAYrtwbjxce0KMQFI61lUNHH3eJYnW3G1mN9Ii9CnRNKSoROSt/7bA2DsQkBD11Y
 5tSZag73T83p/v8+vXEosN+zf41dATNTP3E3pLzGWOjabtm01e5I25FhiT5BgWog
 WshcSKhIKESuek/zyg/6TfDCPHKFmFFnX+itUyzDP1tTT5o8Ij307QIaJqAQR/CC
 Jq+q1HL1u5SDOogWrd74cQG9RDGFIT0eLTu1SAnoRN3foj+IpE8DEF+4FjEI1Zk7
 qVHZzds=
 =+zy6
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmeJEVYACgkQYKtH/8kJ
 UidE9Q/9GDSLN1ZzsOa8z9xf33IpH9RAWZ2Ir//WnVlMgPpp04P1S87qA6CUNjIN
 c/j9jDSKQoullQa06C7ON6DkyZr8wYrxlOYQ8Dh5bq54vXB5JS7z0r/4+H759CnJ
 JtF5aUpcY2ubAsCtmbA86ex2Yu4TwSc24RmMUUMO3thh3JtQiUxkDFEmMLzhSKMU
 C6bl5pT9YlGPwnVo105zXK687x67YdT7S/Foi291lDGr2PlJeGpH7ZakDgn5/S1h
 J4g2LytSyUyrGLNFq30t8wTfBBgLyjuVQstBm5k7ff/GuY2wowMZvBVAS/4Mm07D
 YoeLY9vq4Rvx+CrrFRem0bptLSAp7IIfO1zLpJUnPoUl50vJi3BIq/VCEJeajTEg
 Pw2tFR5SlaC2uu3XH6jOXHVLVH7hrUElOr0usdklxhnKFogymz75da891ZPK56KC
 ZYJkNagqrFcZgPoSXXaijzZZ3q3uWKXL4olPqjUKAx7FHX8RLTrSWelAxSwYQ33B
 L3jDQ9v1LQCnxyAnZBPDjBxxnI8KdxyGRv9iC0lTaxVkyxgawIGM3mbpfl1PF8uN
 zmqB+42BEeAudupEAVZuKph2vDaSWPS9bG91yzuZxY+a31Myx87Wog7vQ/LU1PX0
 IS45Ji6Nv5+SNdi9NO9GY9h1pJYu/wzK4Fmq2CRn4YJtF7tABOQ=
 =zhiA
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-dt-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt

Allwinner Device Tree changes for 6.14

- Add support for DMA engine and audio codec on F1C100s
  and enable audio codec on Lichee Pi Nano
- Add syscon and SRAM nodes for A100
- Enable CPU DVFS for Tanix TX1
- Explicitly configure TCON0 pixel clock parent according to display
  output used

This includes one commit shared with the clock tree

    dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI

which adds the macros for the TCON0 pixel clock parents.

* tag 'sunxi-dt-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a64: explicitly assign clock parent for TCON0
  dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
  arm64: dts: allwinner: h313: enable DVFS for Tanix TX1
  arm64: dts: allwinner: a100: Add syscon nodes
  dt-bindings: sram: sunxi-sram: Add A100 compatible
  ARM: dts: suniv: f1c100s: Activate Audio Codec for Lichee Pi Nano
  ARM: dts: suniv: f1c100s: Add support for Audio Codec
  ARM: dts: suniv: f1c100s: Add support for DMA

Link: https://lore.kernel.org/r/Z36h2FwUxro8rouO@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-01-16 15:01:58 +01:00
commit 36ad66238e
9 changed files with 77 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
View File

@ -47,7 +47,9 @@ properties:
- const: allwinner,sun8i-v3s-system-control
- const: allwinner,sun8i-h3-system-control
- items:
- const: allwinner,sun50i-h6-system-control
- enum:
- allwinner,sun50i-a100-system-control
- allwinner,sun50i-h6-system-control
- const: allwinner,sun50i-a64-system-control
reg:

8
arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts
View File

@ -62,6 +62,14 @@ &uart0 {
status = "okay";
};
&codec {
allwinner,audio-routing =
"Headphone", "HP",
"Headphone", "HPCOM",
"MIC", "Mic";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";

24
arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
#include <dt-bindings/dma/sun4i-a10.h>
/ {
#address-cells = <1>;
@ -159,6 +160,15 @@ usbphy: phy@1c13400 {
status = "disabled";
};
dma: dma-controller@1c02000 {
compatible = "allwinner,suniv-f1c100s-dma";
reg = <0x01c02000 0x1000>;
interrupts = <18>;
clocks = <&ccu CLK_BUS_DMA>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <2>;
};
ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>;
@ -326,5 +336,19 @@ uart2: serial@1c25800 {
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
codec: codec@1c23c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,suniv-f1c100s-codec";
reg = <0x01c23c00 0x400>;
interrupts = <21>;
clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
clock-names = "apb", "codec";
dmas = <&dma SUN4I_DMA_NORMAL 12>,
<&dma SUN4I_DMA_NORMAL 12>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_CODEC>;
status = "disabled";
};
};
};

33
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
View File

@ -101,6 +101,39 @@ soc {
#size-cells = <1>;
ranges = <0 0 0 0x3fffffff>;
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-a100-system-control",
"allwinner,sun50i-a64-system-control";
reg = <0x03000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_a1: sram@20000 {
compatible = "mmio-sram";
reg = <0x00020000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00020000 0x4000>;
};
sram_c: sram@24000 {
compatible = "mmio-sram";
reg = <0x024000 0x21000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x024000 0x21000>;
};
sram_a2: sram@100000 {
compatible = "mmio-sram";
reg = <0x0100000 0x14000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0100000 0x14000>;
};
};
ccu: clock@3001000 {
compatible = "allwinner,sun50i-a100-ccu";
reg = <0x03001000 0x1000>;

2
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
View File

@ -390,6 +390,8 @@ &sound {
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@ -369,6 +369,8 @@ &sound {
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -445,6 +445,8 @@ tcon0: lcd-controller@1c0c000 {
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_MIPI>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";

1
arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts
View File

@ -6,6 +6,7 @@
/dts-v1/;
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

2
include/dt-bindings/clock/sun50i-a64-ccu.h
View File

@ -44,7 +44,9 @@
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_PERIPH0 11
#define CLK_PLL_MIPI 17
#define CLK_CPUX 21
#define CLK_BUS_MIPI_DSI 28