github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-14 16:10:02 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/xe/xe_gt_idle: Add CCS to the powergating info print

Browse Source 
While reading the main GT powergating info from debugfs, include both
RCS and CCS engine masks.

Fixes: 0914c1e45d ("drm/xe/xe_gt_idle: add debugfs entry for powergating info")
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20260819073457.1812722-2-balasubramani.vivekanandan@intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 8899e413c5ab85443ec9bbc50cffe924c6b596de)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Balasubramani Vivekanandan 2026-08-19 13:04:58 +05:30 committed by Rodrigo Vivi
parent f0feab6e9e
commit 369ba0d1ef
No known key found for this signature in database
GPG Key ID: FA625F640EEB13CA
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/xe/xe_gt_idle.c
View File

@ -248,7 +248,8 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
pg_status = xe_mmio_read32(&gt->mmio, POWERGATE_DOMAIN_STATUS);
}
if (gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK) {
if (gt->info.engine_mask &
(XE_HW_ENGINE_RCS_MASK | XE_HW_ENGINE_CCS_MASK)) {
drm_printf(p, "Render Power Gating Enabled: %s\n",
str_yes_no(pg_enabled & RENDER_POWERGATE_ENABLE));