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drm/msm/a6xx: Resolve the meaning of AMSBC

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The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
as a separate field.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660967/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Konrad Dybcio 2025-06-26 11:02:32 +02:00 committed by Rob Clark
parent 560c98b4a4
commit 367380d2b5
1 changed files with 3 additions and 9 deletions
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12
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -636,21 +636,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a621(gpu)) {
gpu->ubwc_config.highest_bank_bit = 13;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
}
if (adreno_is_a623(gpu)) {
gpu->ubwc_config.highest_bank_bit = 16;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a640_family(gpu))
gpu->ubwc_config.amsbc = 1;
if (adreno_is_a680(gpu))
gpu->ubwc_config.macrotile_mode = 1;
@ -661,7 +656,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
gpu->ubwc_config.highest_bank_bit = 16;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
@ -669,7 +663,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a663(gpu)) {
gpu->ubwc_config.highest_bank_bit = 13;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
@ -678,7 +671,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_7c3(gpu)) {
gpu->ubwc_config.highest_bank_bit = 14;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
@ -694,6 +686,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
/*
* We subtract 13 from the highest bank bit (13 is the minimum value
* allowed by hw) and write the lowest two bits of the remaining value
@ -701,6 +694,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
*/
BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
@ -709,7 +703,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
level2_swizzling_dis << 12 |
adreno_gpu->ubwc_config.rgb565_predicator << 11 |
hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 |
hbb_hi << 10 | amsbc << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
hbb_lo << 1 | ubwc_mode);