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ARM: dts: nuvoton: Add UDC nodes

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The driver support was already added but we are missing the nodes in our
common devicetree.

Signed-off-by: William A. Kennington III <william@wkennington.com>
Link: https://patch.msgid.link/20250401235630.3220150-1-william@wkennington.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
This commit is contained in:
William A. Kennington III 2025-04-01 16:56:30 -07:00 committed by Andrew Jeffery
parent f0538cc677
commit 366c846abf
2 changed files with 136 additions and 0 deletions
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71
arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi
View File

@ -99,6 +99,11 @@ rst: rst@801000 {
};
};
udc0_phy: usb-phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
@ -186,6 +191,72 @@ fiux: spi@fb001000 {
status = "disabled";
};
udc5: usb@f0835000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0835000 0x1000
0xfffd2800 0x800>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc6: usb@f0836000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0836000 0x1000
0xfffd3000 0x800>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc7: usb@f0837000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0837000 0x1000
0xfffd3800 0x800>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc8: usb@f0838000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0838000 0x1000
0xfffd4000 0x800>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc9: usb@f0839000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0839000 0x1000
0xfffd4800 0x800>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
nuvoton,sysgcr = <&gcr>;
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;

65
arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi
View File

@ -58,5 +58,70 @@ gmac1: eth@f0804000 {
&rg2mdio_pins>;
status = "disabled";
};
udc0: usb@f0830000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0830000 0x1000
0xfffd0000 0x800>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc1: usb@f0831000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0831000 0x1000
0xfffd0800 0x800>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc2: usb@f0832000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0832000 0x1000
0xfffd1000 0x800>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc3: usb@f0833000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0833000 0x1000
0xfffd1800 0x800>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
udc4: usb@f0834000 {
compatible = "nuvoton,npcm750-udc";
reg = <0xf0834000 0x1000
0xfffd2000 0x800>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM7XX_CLK_SU>;
clock-names = "clk_usb_bridge";
phys = <&udc0_phy>;
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "disabled";
};
};
};