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x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file
Parent commit decoupled amd_northbridge out of _cpuid4_info_regs, where it was merely "parked" there until ci_info_init() can store it in the private pointer of the <linux/cacheinfo.h> API. Given that decoupling, move the AMD-specific L3 cache_disable_0/1 sysfs code from the generic (and already extremely convoluted) x86/cacheinfo code into its own file. Compile the file only if CONFIG_AMD_NB and CONFIG_SYSFS are both enabled, which mirrors the existing logic. Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250324133324.23458-14-darwi@linutronix.de
This commit is contained in:
Ahmed S. Darwish
Ingo Molnar
parent
c58ed2d4da
commit
365e960d29
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@ -38,6 +38,9 @@ obj-y += intel.o tsx.o
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obj-$(CONFIG_PM) += intel_epb.o
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endif
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obj-$(CONFIG_CPU_SUP_AMD) += amd.o
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ifeq ($(CONFIG_AMD_NB)$(CONFIG_SYSFS),yy)
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obj-y += amd_cache_disable.o
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endif
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obj-$(CONFIG_CPU_SUP_HYGON) += hygon.o
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obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
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obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
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301
arch/x86/kernel/cpu/amd_cache_disable.c
Normal file
301
arch/x86/kernel/cpu/amd_cache_disable.c
Normal file
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@ -0,0 +1,301 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* AMD L3 cache_disable_{0,1} sysfs handling
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* Documentation/ABI/testing/sysfs-devices-system-cpu
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*/
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#include <linux/cacheinfo.h>
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#include <linux/capability.h>
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#include <linux/pci.h>
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#include <linux/sysfs.h>
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#include <asm/amd_nb.h>
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#include "cpu.h"
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/*
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* L3 cache descriptors
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*/
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static void amd_calc_l3_indices(struct amd_northbridge *nb)
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{
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struct amd_l3_cache *l3 = &nb->l3_cache;
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unsigned int sc0, sc1, sc2, sc3;
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u32 val = 0;
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pci_read_config_dword(nb->misc, 0x1C4, &val);
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/* calculate subcache sizes */
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l3->subcaches[0] = sc0 = !(val & BIT(0));
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l3->subcaches[1] = sc1 = !(val & BIT(4));
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if (boot_cpu_data.x86 == 0x15) {
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l3->subcaches[0] = sc0 += !(val & BIT(1));
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l3->subcaches[1] = sc1 += !(val & BIT(5));
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}
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l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9));
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l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
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l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
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}
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/*
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* check whether a slot used for disabling an L3 index is occupied.
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* @l3: L3 cache descriptor
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* @slot: slot number (0..1)
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*
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* @returns: the disabled index if used or negative value if slot free.
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*/
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static int amd_get_l3_disable_slot(struct amd_northbridge *nb, unsigned int slot)
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{
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unsigned int reg = 0;
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pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®);
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/* check whether this slot is activated already */
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if (reg & (3UL << 30))
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return reg & 0xfff;
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return -1;
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}
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static ssize_t show_cache_disable(struct cacheinfo *ci, char *buf, unsigned int slot)
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{
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int index;
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struct amd_northbridge *nb = ci->priv;
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index = amd_get_l3_disable_slot(nb, slot);
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if (index >= 0)
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return sprintf(buf, "%d\n", index);
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return sprintf(buf, "FREE\n");
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}
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#define SHOW_CACHE_DISABLE(slot) \
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static ssize_t \
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cache_disable_##slot##_show(struct device *dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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struct cacheinfo *ci = dev_get_drvdata(dev); \
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return show_cache_disable(ci, buf, slot); \
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}
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SHOW_CACHE_DISABLE(0)
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SHOW_CACHE_DISABLE(1)
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static void amd_l3_disable_index(struct amd_northbridge *nb, int cpu,
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unsigned int slot, unsigned long idx)
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{
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int i;
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idx |= BIT(30);
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/*
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* disable index in all 4 subcaches
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*/
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for (i = 0; i < 4; i++) {
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u32 reg = idx | (i << 20);
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if (!nb->l3_cache.subcaches[i])
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continue;
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pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);
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/*
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* We need to WBINVD on a core on the node containing the L3
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* cache which indices we disable therefore a simple wbinvd()
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* is not sufficient.
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*/
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wbinvd_on_cpu(cpu);
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reg |= BIT(31);
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pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);
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}
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}
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/*
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* disable a L3 cache index by using a disable-slot
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*
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* @l3: L3 cache descriptor
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* @cpu: A CPU on the node containing the L3 cache
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* @slot: slot number (0..1)
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* @index: index to disable
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*
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* @return: 0 on success, error status on failure
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*/
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static int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu,
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unsigned int slot, unsigned long index)
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{
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int ret = 0;
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/* check if @slot is already used or the index is already disabled */
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ret = amd_get_l3_disable_slot(nb, slot);
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if (ret >= 0)
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return -EEXIST;
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if (index > nb->l3_cache.indices)
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return -EINVAL;
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/* check whether the other slot has disabled the same index already */
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if (index == amd_get_l3_disable_slot(nb, !slot))
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return -EEXIST;
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amd_l3_disable_index(nb, cpu, slot, index);
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return 0;
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}
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static ssize_t store_cache_disable(struct cacheinfo *ci, const char *buf,
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size_t count, unsigned int slot)
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{
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struct amd_northbridge *nb = ci->priv;
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unsigned long val = 0;
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int cpu, err = 0;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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cpu = cpumask_first(&ci->shared_cpu_map);
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if (kstrtoul(buf, 10, &val) < 0)
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return -EINVAL;
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err = amd_set_l3_disable_slot(nb, cpu, slot, val);
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if (err) {
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if (err == -EEXIST)
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pr_warn("L3 slot %d in use/index already disabled!\n",
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slot);
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return err;
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}
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return count;
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}
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#define STORE_CACHE_DISABLE(slot) \
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static ssize_t \
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cache_disable_##slot##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *buf, size_t count) \
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{ \
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struct cacheinfo *ci = dev_get_drvdata(dev); \
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return store_cache_disable(ci, buf, count, slot); \
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}
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STORE_CACHE_DISABLE(0)
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STORE_CACHE_DISABLE(1)
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static ssize_t subcaches_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct cacheinfo *ci = dev_get_drvdata(dev);
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int cpu = cpumask_first(&ci->shared_cpu_map);
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return sprintf(buf, "%x\n", amd_get_subcaches(cpu));
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}
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static ssize_t subcaches_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct cacheinfo *ci = dev_get_drvdata(dev);
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int cpu = cpumask_first(&ci->shared_cpu_map);
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unsigned long val;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (kstrtoul(buf, 16, &val) < 0)
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return -EINVAL;
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if (amd_set_subcaches(cpu, val))
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return -EINVAL;
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return count;
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}
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static DEVICE_ATTR_RW(cache_disable_0);
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static DEVICE_ATTR_RW(cache_disable_1);
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static DEVICE_ATTR_RW(subcaches);
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static umode_t cache_private_attrs_is_visible(struct kobject *kobj,
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struct attribute *attr, int unused)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct cacheinfo *ci = dev_get_drvdata(dev);
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umode_t mode = attr->mode;
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if (!ci->priv)
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return 0;
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if ((attr == &dev_attr_subcaches.attr) &&
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amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return mode;
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if ((attr == &dev_attr_cache_disable_0.attr ||
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attr == &dev_attr_cache_disable_1.attr) &&
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amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
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return mode;
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return 0;
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}
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static struct attribute_group cache_private_group = {
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.is_visible = cache_private_attrs_is_visible,
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};
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static void init_amd_l3_attrs(void)
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{
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static struct attribute **amd_l3_attrs;
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int n = 1;
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if (amd_l3_attrs) /* already initialized */
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return;
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if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
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n += 2;
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if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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n += 1;
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amd_l3_attrs = kcalloc(n, sizeof(*amd_l3_attrs), GFP_KERNEL);
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if (!amd_l3_attrs)
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return;
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n = 0;
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if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) {
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amd_l3_attrs[n++] = &dev_attr_cache_disable_0.attr;
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amd_l3_attrs[n++] = &dev_attr_cache_disable_1.attr;
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}
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if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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amd_l3_attrs[n++] = &dev_attr_subcaches.attr;
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cache_private_group.attrs = amd_l3_attrs;
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}
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const struct attribute_group *cache_get_priv_group(struct cacheinfo *ci)
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{
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struct amd_northbridge *nb = ci->priv;
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if (ci->level < 3 || !nb)
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return NULL;
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if (nb && nb->l3_cache.indices)
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init_amd_l3_attrs();
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return &cache_private_group;
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}
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struct amd_northbridge *amd_init_l3_cache(int index)
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{
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struct amd_northbridge *nb;
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int node;
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/* only for L3, and not in virtualized environments */
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if (index < 3)
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return NULL;
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node = topology_amd_node_id(smp_processor_id());
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nb = node_to_amd_nb(node);
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if (nb && !nb->l3_cache.indices)
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amd_calc_l3_indices(nb);
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return nb;
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}
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@ -9,12 +9,9 @@
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*/
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#include <linux/cacheinfo.h>
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#include <linux/capability.h>
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#include <linux/cpu.h>
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#include <linux/cpuhotplug.h>
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#include <linux/pci.h>
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#include <linux/stop_machine.h>
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#include <linux/sysfs.h>
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#include <asm/amd_nb.h>
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#include <asm/cacheinfo.h>
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@ -300,301 +297,6 @@ amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
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(ebx->split.ways_of_associativity + 1) - 1;
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}
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#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)
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/*
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* L3 cache descriptors
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*/
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static void amd_calc_l3_indices(struct amd_northbridge *nb)
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{
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struct amd_l3_cache *l3 = &nb->l3_cache;
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unsigned int sc0, sc1, sc2, sc3;
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u32 val = 0;
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pci_read_config_dword(nb->misc, 0x1C4, &val);
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/* calculate subcache sizes */
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l3->subcaches[0] = sc0 = !(val & BIT(0));
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l3->subcaches[1] = sc1 = !(val & BIT(4));
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if (boot_cpu_data.x86 == 0x15) {
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l3->subcaches[0] = sc0 += !(val & BIT(1));
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l3->subcaches[1] = sc1 += !(val & BIT(5));
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}
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l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9));
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l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
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l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
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}
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/*
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* check whether a slot used for disabling an L3 index is occupied.
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* @l3: L3 cache descriptor
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* @slot: slot number (0..1)
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*
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* @returns: the disabled index if used or negative value if slot free.
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*/
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static int amd_get_l3_disable_slot(struct amd_northbridge *nb, unsigned slot)
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{
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unsigned int reg = 0;
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pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®);
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/* check whether this slot is activated already */
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if (reg & (3UL << 30))
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return reg & 0xfff;
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return -1;
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}
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static ssize_t show_cache_disable(struct cacheinfo *ci, char *buf, unsigned int slot)
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{
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int index;
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struct amd_northbridge *nb = ci->priv;
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index = amd_get_l3_disable_slot(nb, slot);
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if (index >= 0)
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return sprintf(buf, "%d\n", index);
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return sprintf(buf, "FREE\n");
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}
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#define SHOW_CACHE_DISABLE(slot) \
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static ssize_t \
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cache_disable_##slot##_show(struct device *dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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struct cacheinfo *ci = dev_get_drvdata(dev); \
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return show_cache_disable(ci, buf, slot); \
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}
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SHOW_CACHE_DISABLE(0)
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SHOW_CACHE_DISABLE(1)
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static void amd_l3_disable_index(struct amd_northbridge *nb, int cpu,
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unsigned slot, unsigned long idx)
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{
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int i;
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idx |= BIT(30);
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/*
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* disable index in all 4 subcaches
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*/
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for (i = 0; i < 4; i++) {
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u32 reg = idx | (i << 20);
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if (!nb->l3_cache.subcaches[i])
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continue;
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pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);
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/*
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* We need to WBINVD on a core on the node containing the L3
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* cache which indices we disable therefore a simple wbinvd()
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* is not sufficient.
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*/
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wbinvd_on_cpu(cpu);
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reg |= BIT(31);
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pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);
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}
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}
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/*
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* disable a L3 cache index by using a disable-slot
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*
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* @l3: L3 cache descriptor
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* @cpu: A CPU on the node containing the L3 cache
|
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* @slot: slot number (0..1)
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* @index: index to disable
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*
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* @return: 0 on success, error status on failure
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*/
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static int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu,
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unsigned slot, unsigned long index)
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{
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int ret = 0;
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/* check if @slot is already used or the index is already disabled */
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ret = amd_get_l3_disable_slot(nb, slot);
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if (ret >= 0)
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return -EEXIST;
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if (index > nb->l3_cache.indices)
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return -EINVAL;
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/* check whether the other slot has disabled the same index already */
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if (index == amd_get_l3_disable_slot(nb, !slot))
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return -EEXIST;
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amd_l3_disable_index(nb, cpu, slot, index);
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return 0;
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}
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static ssize_t store_cache_disable(struct cacheinfo *ci, const char *buf,
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size_t count, unsigned int slot)
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||||
{
|
||||
unsigned long val = 0;
|
||||
int cpu, err = 0;
|
||||
struct amd_northbridge *nb = ci->priv;
|
||||
|
||||
if (!capable(CAP_SYS_ADMIN))
|
||||
return -EPERM;
|
||||
|
||||
cpu = cpumask_first(&ci->shared_cpu_map);
|
||||
|
||||
if (kstrtoul(buf, 10, &val) < 0)
|
||||
return -EINVAL;
|
||||
|
||||
err = amd_set_l3_disable_slot(nb, cpu, slot, val);
|
||||
if (err) {
|
||||
if (err == -EEXIST)
|
||||
pr_warn("L3 slot %d in use/index already disabled!\n",
|
||||
slot);
|
||||
return err;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
#define STORE_CACHE_DISABLE(slot) \
|
||||
static ssize_t \
|
||||
cache_disable_##slot##_store(struct device *dev, \
|
||||
struct device_attribute *attr, \
|
||||
const char *buf, size_t count) \
|
||||
{ \
|
||||
struct cacheinfo *ci = dev_get_drvdata(dev); \
|
||||
return store_cache_disable(ci, buf, count, slot); \
|
||||
}
|
||||
STORE_CACHE_DISABLE(0)
|
||||
STORE_CACHE_DISABLE(1)
|
||||
|
||||
static ssize_t subcaches_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct cacheinfo *ci = dev_get_drvdata(dev);
|
||||
int cpu = cpumask_first(&ci->shared_cpu_map);
|
||||
|
||||
return sprintf(buf, "%x\n", amd_get_subcaches(cpu));
|
||||
}
|
||||
|
||||
static ssize_t subcaches_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct cacheinfo *ci = dev_get_drvdata(dev);
|
||||
int cpu = cpumask_first(&ci->shared_cpu_map);
|
||||
unsigned long val;
|
||||
|
||||
if (!capable(CAP_SYS_ADMIN))
|
||||
return -EPERM;
|
||||
|
||||
if (kstrtoul(buf, 16, &val) < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (amd_set_subcaches(cpu, val))
|
||||
return -EINVAL;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR_RW(cache_disable_0);
|
||||
static DEVICE_ATTR_RW(cache_disable_1);
|
||||
static DEVICE_ATTR_RW(subcaches);
|
||||
|
||||
static umode_t
|
||||
cache_private_attrs_is_visible(struct kobject *kobj,
|
||||
struct attribute *attr, int unused)
|
||||
{
|
||||
struct device *dev = kobj_to_dev(kobj);
|
||||
struct cacheinfo *ci = dev_get_drvdata(dev);
|
||||
umode_t mode = attr->mode;
|
||||
|
||||
if (!ci->priv)
|
||||
return 0;
|
||||
|
||||
if ((attr == &dev_attr_subcaches.attr) &&
|
||||
amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
||||
return mode;
|
||||
|
||||
if ((attr == &dev_attr_cache_disable_0.attr ||
|
||||
attr == &dev_attr_cache_disable_1.attr) &&
|
||||
amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
|
||||
return mode;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct attribute_group cache_private_group = {
|
||||
.is_visible = cache_private_attrs_is_visible,
|
||||
};
|
||||
|
||||
static void init_amd_l3_attrs(void)
|
||||
{
|
||||
int n = 1;
|
||||
static struct attribute **amd_l3_attrs;
|
||||
|
||||
if (amd_l3_attrs) /* already initialized */
|
||||
return;
|
||||
|
||||
if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
|
||||
n += 2;
|
||||
if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
||||
n += 1;
|
||||
|
||||
amd_l3_attrs = kcalloc(n, sizeof(*amd_l3_attrs), GFP_KERNEL);
|
||||
if (!amd_l3_attrs)
|
||||
return;
|
||||
|
||||
n = 0;
|
||||
if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) {
|
||||
amd_l3_attrs[n++] = &dev_attr_cache_disable_0.attr;
|
||||
amd_l3_attrs[n++] = &dev_attr_cache_disable_1.attr;
|
||||
}
|
||||
if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
||||
amd_l3_attrs[n++] = &dev_attr_subcaches.attr;
|
||||
|
||||
cache_private_group.attrs = amd_l3_attrs;
|
||||
}
|
||||
|
||||
const struct attribute_group *
|
||||
cache_get_priv_group(struct cacheinfo *ci)
|
||||
{
|
||||
struct amd_northbridge *nb = ci->priv;
|
||||
|
||||
if (ci->level < 3 || !nb)
|
||||
return NULL;
|
||||
|
||||
if (nb && nb->l3_cache.indices)
|
||||
init_amd_l3_attrs();
|
||||
|
||||
return &cache_private_group;
|
||||
}
|
||||
|
||||
static struct amd_northbridge *amd_init_l3_cache(int index)
|
||||
{
|
||||
struct amd_northbridge *nb;
|
||||
int node;
|
||||
|
||||
/* only for L3, and not in virtualized environments */
|
||||
if (index < 3)
|
||||
return NULL;
|
||||
|
||||
node = topology_amd_node_id(smp_processor_id());
|
||||
nb = node_to_amd_nb(node);
|
||||
if (nb && !nb->l3_cache.indices)
|
||||
amd_calc_l3_indices(nb);
|
||||
|
||||
return nb;
|
||||
}
|
||||
#else
|
||||
static struct amd_northbridge *amd_init_l3_cache(int index)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif /* CONFIG_AMD_NB && CONFIG_SYSFS */
|
||||
|
||||
/*
|
||||
* Fill passed _cpuid4_info_regs structure.
|
||||
* Intel-only code paths should pass NULL for the amd_northbridge
|
||||
|
|
|
|||
|
|
@ -75,6 +75,15 @@ extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
|
|||
void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id);
|
||||
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c);
|
||||
|
||||
#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)
|
||||
struct amd_northbridge *amd_init_l3_cache(int index);
|
||||
#else
|
||||
static inline struct amd_northbridge *amd_init_l3_cache(int index)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
unsigned int aperfmperf_get_khz(int cpu);
|
||||
void cpu_select_mitigations(void);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user