From 363f97a1ce635b86be7fd263d56a040fbd87bdbb Mon Sep 17 00:00:00 2001 From: Lucas Tanure Date: Sat, 5 Sep 2026 16:32:34 +0100 Subject: [PATCH] clk: meson: t7: don't mark sys_ampipe_nand as critical sys_ampipe_nand clocks the pipeline stage inserted in the bus path between the SD/eMMC controllers and the NIC_MATRIX fabric. It does have identifiable consumers - the three MMC controllers - so marking it critical was the wrong tool: the clock should be referenced from the consumer nodes and claimed by the mmc driver instead. Drop the CLK_IS_CRITICAL flag and update the comment accordingly. sys_am2axi0..2 remain critical as they clock the AXI DMA bus itself and have no single identifiable consumer. Assisted-by: Claude:claude-fable-5 Signed-off-by: Lucas Tanure Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260905153234.133217-5-tanure@linux.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/t7-peripherals.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c index 55d09e78593b..2f429ea86796 100644 --- a/drivers/clk/meson/t7-peripherals.c +++ b/drivers/clk/meson/t7-peripherals.c @@ -945,13 +945,13 @@ static T7_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14, 0); static T7_SYS_PCLK(sys_cec, SYS_CLK_EN0_REG0, 16, 0); static T7_SYS_PCLK(sys_gdc, SYS_CLK_EN0_REG0, 17, 0); static T7_SYS_PCLK(sys_deswarp, SYS_CLK_EN0_REG0, 18, 0); -/* - * NOTE: sys_ampipe_nand and sys_am2axi0..2 provide the clock to the AXI bus - * used for DMA between the peripherals and the DRAM. After the clocks are - * disabled, a device that starts a transfer cannot complete it. - */ -static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, CLK_IS_CRITICAL); +static T7_SYS_PCLK(sys_ampipe_nand, SYS_CLK_EN0_REG0, 19, 0); static T7_SYS_PCLK(sys_ampipe_eth, SYS_CLK_EN0_REG0, 20, 0); +/* + * NOTE: sys_am2axi0..2 provide the clock to the AXI bus used for DMA between + * the peripherals and the DRAM. After the clocks are disabled, a device that + * starts a transfer cannot complete it. + */ static T7_SYS_PCLK(sys_am2axi0, SYS_CLK_EN0_REG0, 21, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi1, SYS_CLK_EN0_REG0, 22, CLK_IS_CRITICAL); static T7_SYS_PCLK(sys_am2axi2, SYS_CLK_EN0_REG0, 23, CLK_IS_CRITICAL);