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phy/rockchip: typec: improved handling of typec_dp_phy_config()
Change-Id: I61ca43ffe7fe85e041fb3ed66ba1d59f515770d9 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
Tao Huang
parent
08aea10ffd
commit
363e47c6aa
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@ -295,13 +295,37 @@
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#define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2)
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#define RX_DIAG_SC2C_DELAY (0x81e1 << 2)
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#define PMA_LANE_CFG (0xc000 << 2)
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#define PHY_PMA_LANE_CFG (0xc000 << 2)
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#define PMA_LANE3_DP_LANE_SEL(x) (((x) & 0x3) << 14)
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#define PMA_LANE3_INTERFACE_SEL(x) (((x) & 0x1) << 12)
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#define PMA_LANE2_DP_LANE_SEL(x) (((x) & 0x3) << 10)
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#define PMA_LANE2_INTERFACE_SEL(x) (((x) & 0x1) << 8)
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#define PMA_LANE1_DP_LANE_SEL(x) (((x) & 0x3) << 6)
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#define PMA_LANE1_INTERFACE_SEL(x) (((x) & 0x1) << 4)
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#define PMA_LANE0_DP_LANE_SEL(x) (((x) & 0x3) << 2)
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#define PMA_LANE0_INTERFACE_SEL(x) (((x) & 0x1) << 0)
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#define PIPE_CMN_CTRL1 (0xc001 << 2)
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#define PIPE_CMN_CTRL2 (0xc002 << 2)
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#define PIPE_COM_LOCK_CFG1 (0xc003 << 2)
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#define PIPE_COM_LOCK_CFG2 (0xc004 << 2)
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#define PIPE_RCV_DET_INH (0xc005 << 2)
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#define DP_MODE_CTL (0xc008 << 2)
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#define PHY_DP_MODE_CTL (0xc008 << 2)
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#define PHY_DP_LANE_DISABLE GENMASK(15, 12)
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#define PHY_DP_LANE_3_DISABLE BIT(15)
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#define PHY_DP_LANE_2_DISABLE BIT(14)
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#define PHY_DP_LANE_1_DISABLE BIT(13)
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#define PHY_DP_LANE_0_DISABLE BIT(12)
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#define PHY_DP_POWER_STATE_ACK_MASK GENMASK(7, 4)
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#define PHY_DP_POWER_STATE_ACK_SHIFT 4
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#define PHY_DP_POWER_STATE_MASK GENMASK(3, 0)
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#define PHY_DP_CLK_CTL (0xc009 << 2)
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#define DP_PLL_CLOCK_ENABLE_ACK BIT(3)
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#define DP_PLL_CLOCK_ENABLE_MASK BIT(2)
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#define DP_PLL_CLOCK_DISABLE 0
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#define DP_PLL_READY BIT(1)
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#define DP_PLL_ENABLE_MASK BIT(0)
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#define DP_PLL_ENABLE BIT(0)
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#define DP_PLL_DISABLE 0
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#define DP_CLK_CTL (0xc009 << 2)
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#define STS (0xc00F << 2)
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#define PHY_ISO_CMN_CTRL (0xc010 << 2)
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@ -468,6 +492,283 @@ static const struct phy_config tcphy_default_config[3][4] = {
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{ .swing = 0, .pe = 0 } },
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};
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enum phy_dp_power_state {
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PHY_DP_POWER_STATE_DISABLED = -1,
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PHY_DP_POWER_STATE_A0,
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PHY_DP_POWER_STATE_A1,
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PHY_DP_POWER_STATE_A2,
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PHY_DP_POWER_STATE_A3,
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};
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static int tcphy_dp_set_power_state(struct rockchip_typec_phy *tcphy,
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enum phy_dp_power_state state)
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{
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u32 ack, reg, sts = BIT(state);
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int ret;
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/*
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* Power state changes must not be requested until after the cmn_ready
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* signal has gone active.
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*/
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reg = readl(tcphy->base + PMA_CMN_CTRL1);
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if (!(reg & CMN_READY)) {
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dev_err(tcphy->dev, "cmn_ready in the inactive state\n");
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return -EINVAL;
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}
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reg = readl(tcphy->base + PHY_DP_MODE_CTL);
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reg &= ~PHY_DP_POWER_STATE_MASK;
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reg |= sts;
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writel(reg, tcphy->base + PHY_DP_MODE_CTL);
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ret = readl_poll_timeout(tcphy->base + PHY_DP_MODE_CTL,
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ack, (((ack & PHY_DP_POWER_STATE_ACK_MASK) >>
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PHY_DP_POWER_STATE_ACK_SHIFT) == sts), 10,
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PHY_MODE_SET_TIMEOUT);
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if (ret < 0) {
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dev_err(tcphy->dev, "failed to enter power state %d\n", state);
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return ret;
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}
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return 0;
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}
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enum {
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PHY_DP_LANE_0,
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PHY_DP_LANE_1,
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PHY_DP_LANE_2,
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PHY_DP_LANE_3,
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};
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enum {
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PMA_IF_PIPE_PCS,
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PMA_IF_PHY_DP,
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};
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/*
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* For the TypeC PHY, the 4 lanes are mapping to the USB TypeC receptacle pins
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* as follows:
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* -------------------------------------------------------------------
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* PHY Lanes/Module Pins TypeC Receptacle Pins
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* -------------------------------------------------------------------
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* Lane0 (tx_p/m_ln_0) TX1+/TX1- (pins A2/A3)
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* Lane1 (tx_rx_p/m_ln_1) RX1+/RX1- (pins B11/B10)
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* Lane2 (tx_rx_p/m_ln_2) RX2+/RX2- (pins A11/A10)
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* Lane3 (tx_p/m_ln_3) TX2+/TX2- (pins B2/B3)
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* -------------------------------------------------------------------
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*
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* USB and DP lanes mapping to TypeC PHY lanes for each of pin assignment
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* options (normal connector orientation) described in the VESA DisplayPort
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* Alt Mode on USB TypeC Standard as follows:
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*
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* ----------------------------------------------------------------------
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* PHY Lanes A B C D E F
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* ----------------------------------------------------------------------
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* 0 ML1 SSTX ML2 SSTX ML2 SSTX
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* 1 ML3 SSRX ML3 SSRX ML3 SSRX
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* 2 ML2 ML1 ML0 ML0 ML0 ML0
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* 3 ML0 ML0 ML1 ML1 ML1 ML1
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* ----------------------------------------------------------------------
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*/
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static void tcphy_set_lane_mapping(struct rockchip_typec_phy *tcphy, u8 mode)
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{
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/*
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* The PHY_PMA_LANE_CFG register is used to select whether a PMA lane
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* is mapped for USB or PHY DP. The PHY_PMA_LANE_CFG register is
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* configured based on a normal connector orientation. Logic in the
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* PHY automatically handles the flipped connector case based on the
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* setting of orientation of TypeC PHY.
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*/
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if (mode == MODE_DFP_DP) {
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/* This maps to VESA DP Alt Mode pin assignments C and E. */
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writel(PMA_LANE3_DP_LANE_SEL(PHY_DP_LANE_1) |
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PMA_LANE3_INTERFACE_SEL(PMA_IF_PHY_DP) |
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PMA_LANE2_DP_LANE_SEL(PHY_DP_LANE_0) |
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PMA_LANE2_INTERFACE_SEL(PMA_IF_PHY_DP) |
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PMA_LANE1_DP_LANE_SEL(PHY_DP_LANE_3) |
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PMA_LANE1_INTERFACE_SEL(PMA_IF_PHY_DP) |
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PMA_LANE0_DP_LANE_SEL(PHY_DP_LANE_2) |
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PMA_LANE0_INTERFACE_SEL(PMA_IF_PHY_DP),
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tcphy->base + PHY_PMA_LANE_CFG);
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} else {
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/* This maps to VESA DP Alt Mode pin assignments D and F. */
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writel(PMA_LANE3_DP_LANE_SEL(PHY_DP_LANE_1) |
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PMA_LANE3_INTERFACE_SEL(PMA_IF_PHY_DP) |
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PMA_LANE2_DP_LANE_SEL(PHY_DP_LANE_0) |
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PMA_LANE2_INTERFACE_SEL(PMA_IF_PHY_DP) |
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PMA_LANE1_INTERFACE_SEL(PMA_IF_PIPE_PCS) |
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PMA_LANE0_INTERFACE_SEL(PMA_IF_PIPE_PCS),
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tcphy->base + PHY_PMA_LANE_CFG);
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}
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}
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static int tcphy_dp_set_lane_count(struct rockchip_typec_phy *tcphy,
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u8 lane_count)
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{
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u32 reg;
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/*
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* In cases where fewer than the configured number of DP lanes are
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* being used. PHY_DP_MODE_CTL[15:12] must be set to disable and
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* power-down the unused PHY DP lanes (and their mapped PMA lanes).
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* Set the bit ([15:12]) associated with each DP PHY lane(s) to be
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* disabled.
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*/
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reg = readl(tcphy->base + PHY_DP_MODE_CTL);
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reg |= PHY_DP_LANE_DISABLE;
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switch (lane_count) {
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case 4:
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reg &= ~(PHY_DP_LANE_3_DISABLE | PHY_DP_LANE_2_DISABLE |
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PHY_DP_LANE_1_DISABLE | PHY_DP_LANE_0_DISABLE);
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break;
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case 2:
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reg &= ~(PHY_DP_LANE_1_DISABLE | PHY_DP_LANE_0_DISABLE);
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break;
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case 1:
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reg &= ~PHY_DP_LANE_0_DISABLE;
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break;
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default:
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return -EINVAL;
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}
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writel(reg, tcphy->base + PHY_DP_MODE_CTL);
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tcphy->dp.lane_count = lane_count;
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return 0;
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}
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static int tcphy_dp_set_link_rate(struct rockchip_typec_phy *tcphy,
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int link_rate)
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{
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const struct phy_reg *phy_cfg;
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u32 cmn_diag_hsclk_sel, phy_dp_clk_ctl, reg;
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u32 i, cfg_size;
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int ret;
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/* Place the PHY lanes in the A3 power state. */
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ret = tcphy_dp_set_power_state(tcphy, PHY_DP_POWER_STATE_A3);
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if (ret) {
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dev_err(tcphy->dev, "failed to enter A3 state: %d\n", ret);
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return ret;
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}
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/* Gate the PLL clocks from PMA */
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reg = readl(tcphy->base + PHY_DP_CLK_CTL);
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reg &= ~DP_PLL_CLOCK_ENABLE_MASK;
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reg |= DP_PLL_CLOCK_DISABLE;
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writel(reg, tcphy->base + PHY_DP_CLK_CTL);
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ret = readl_poll_timeout(tcphy->base + PHY_DP_CLK_CTL, reg,
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!(reg & DP_PLL_CLOCK_ENABLE_ACK),
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10, PHY_MODE_SET_TIMEOUT);
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if (ret) {
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dev_err(tcphy->dev, "wait DP PLL clock disabled timeout\n");
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return ret;
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}
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/* Disable the PLL */
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reg = readl(tcphy->base + PHY_DP_CLK_CTL);
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reg &= ~DP_PLL_ENABLE_MASK;
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reg |= DP_PLL_DISABLE;
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writel(reg, tcphy->base + PHY_DP_CLK_CTL);
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ret = readl_poll_timeout(tcphy->base + PHY_DP_CLK_CTL, reg,
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!(reg & DP_PLL_READY),
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10, PHY_MODE_SET_TIMEOUT);
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if (ret) {
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dev_err(tcphy->dev, "wait DP PLL not ready timeout\n");
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return ret;
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}
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/* Re-configure PHY registers for the new data rate */
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cmn_diag_hsclk_sel = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
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cmn_diag_hsclk_sel &= ~(GENMASK(5, 4) | GENMASK(1, 0));
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phy_dp_clk_ctl = readl(tcphy->base + PHY_DP_CLK_CTL);
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phy_dp_clk_ctl &= ~(GENMASK(15, 12) | GENMASK(11, 8));
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switch (link_rate) {
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case 162000:
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cmn_diag_hsclk_sel |= (3 << 4) | (0 << 0);
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phy_dp_clk_ctl |= (2 << 12) | (4 << 8);
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phy_cfg = dp_pll_rbr_cfg;
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cfg_size = ARRAY_SIZE(dp_pll_rbr_cfg);
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break;
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case 270000:
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cmn_diag_hsclk_sel |= (3 << 4) | (0 << 0);
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phy_dp_clk_ctl |= (2 << 12) | (4 << 8);
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phy_cfg = dp_pll_hbr_cfg;
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cfg_size = ARRAY_SIZE(dp_pll_hbr_cfg);
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break;
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case 540000:
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cmn_diag_hsclk_sel |= (2 << 4) | (0 << 0);
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phy_dp_clk_ctl |= (1 << 12) | (2 << 8);
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phy_cfg = dp_pll_hbr2_cfg;
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cfg_size = ARRAY_SIZE(dp_pll_hbr2_cfg);
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break;
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default:
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return -EINVAL;
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}
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writel(cmn_diag_hsclk_sel, tcphy->base + CMN_DIAG_HSCLK_SEL);
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writel(phy_dp_clk_ctl, tcphy->base + PHY_DP_CLK_CTL);
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/* load the configuration of PLL1 */
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for (i = 0; i < cfg_size; i++)
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writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr);
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/* Enable the PLL */
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reg = readl(tcphy->base + PHY_DP_CLK_CTL);
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reg &= ~DP_PLL_ENABLE_MASK;
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reg |= DP_PLL_ENABLE;
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writel(reg, tcphy->base + PHY_DP_CLK_CTL);
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ret = readl_poll_timeout(tcphy->base + PHY_DP_CLK_CTL, reg,
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reg & DP_PLL_READY,
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10, PHY_MODE_SET_TIMEOUT);
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if (ret < 0) {
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dev_err(tcphy->dev, "wait DP PLL ready timeout\n");
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return ret;
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}
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/* Enable PMA PLL clocks */
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reg = readl(tcphy->base + PHY_DP_CLK_CTL);
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reg &= ~DP_PLL_CLOCK_ENABLE_MASK;
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reg |= DP_PLL_CLOCK_ENABLE;
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writel(reg, tcphy->base + PHY_DP_CLK_CTL);
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ret = readl_poll_timeout(tcphy->base + PHY_DP_CLK_CTL, reg,
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reg & DP_PLL_CLOCK_ENABLE_ACK,
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10, PHY_MODE_SET_TIMEOUT);
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if (ret) {
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dev_err(tcphy->dev, "wait DP PLL clock enabled timeout\n");
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return ret;
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}
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/* The PMA must go through the A2 power state upon a data rate change */
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ret = tcphy_dp_set_power_state(tcphy, PHY_DP_POWER_STATE_A2);
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if (ret) {
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dev_err(tcphy->dev, "failed to enter A2 state: %d\n", ret);
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return ret;
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}
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/* change the PHY power state to A0 */
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ret = tcphy_dp_set_power_state(tcphy, PHY_DP_POWER_STATE_A0);
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if (ret) {
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dev_err(tcphy->dev, "failed to enter A0 state: %d\n", ret);
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return ret;
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}
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tcphy->dp.link_rate = link_rate;
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return 0;
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}
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static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy)
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{
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u32 i, rdata;
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@ -535,12 +836,14 @@ static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy, int link_rate)
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}
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clk_ctrl |= DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE;
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writel(clk_ctrl, tcphy->base + DP_CLK_CTL);
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writel(clk_ctrl, tcphy->base + PHY_DP_CLK_CTL);
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writel(hsclk_sel, tcphy->base + CMN_DIAG_HSCLK_SEL);
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/* load the configuration of PLL1 */
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for (i = 0; i < cfg_size; i++)
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writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr);
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tcphy->dp.link_rate = link_rate;
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}
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static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
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@ -792,13 +1095,12 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
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tcphy_dp_aux_set_flip(tcphy);
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tcphy_cfg_24m(tcphy);
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tcphy_set_lane_mapping(tcphy, mode);
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if (mode == MODE_DFP_DP) {
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tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
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for (i = 0; i < 4; i++)
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tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, i);
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writel(PIN_ASSIGN_C_E, tcphy->base + PMA_LANE_CFG);
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} else {
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tcphy_cfg_usb3_pll(tcphy);
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tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
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@ -813,14 +1115,12 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
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tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 2);
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tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 3);
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}
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writel(PIN_ASSIGN_D_F, tcphy->base + PMA_LANE_CFG);
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}
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val = readl(tcphy->base + DP_MODE_CTL);
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val = readl(tcphy->base + PHY_DP_MODE_CTL);
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val &= ~DP_MODE_MASK;
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val |= DP_MODE_ENTER_A2 | DP_LINK_RESET_DEASSERTED;
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writel(val, tcphy->base + DP_MODE_CTL);
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writel(val, tcphy->base + PHY_DP_MODE_CTL);
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reset_control_deassert(tcphy->uphy_rst);
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@ -1055,7 +1355,7 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
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property_enable(tcphy, &cfg->uphy_dp_sel, 1);
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ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
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ret = readx_poll_timeout(readl, tcphy->base + PHY_DP_MODE_CTL,
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val, val & DP_MODE_A2_ACK, 1000,
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PHY_MODE_SET_TIMEOUT);
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if (ret < 0) {
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@ -1066,19 +1366,9 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
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tcphy_dp_aux_calibration(tcphy);
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/* enter A0 mode */
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val = readl(tcphy->base + DP_MODE_CTL);
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val &= ~DP_MODE_MASK;
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val |= DP_MODE_ENTER_A0;
|
||||
writel(val, tcphy->base + DP_MODE_CTL);
|
||||
|
||||
ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
|
||||
val, val & DP_MODE_A0_ACK, 1000,
|
||||
PHY_MODE_SET_TIMEOUT);
|
||||
if (ret < 0) {
|
||||
val &= ~DP_MODE_MASK;
|
||||
val |= DP_MODE_ENTER_A2;
|
||||
writel(val, tcphy->base + DP_MODE_CTL);
|
||||
dev_err(tcphy->dev, "failed to wait TCPHY enter A0\n");
|
||||
ret = tcphy_dp_set_power_state(tcphy, PHY_DP_POWER_STATE_A0);
|
||||
if (ret) {
|
||||
dev_err(tcphy->dev, "failed to enter A0 power state\n");
|
||||
goto power_on_finish;
|
||||
}
|
||||
|
||||
|
|
@ -1095,7 +1385,7 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
|
|||
static int rockchip_dp_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&tcphy->lock);
|
||||
|
||||
|
|
@ -1104,10 +1394,11 @@ static int rockchip_dp_phy_power_off(struct phy *phy)
|
|||
|
||||
tcphy->mode &= ~MODE_DFP_DP;
|
||||
|
||||
val = readl(tcphy->base + DP_MODE_CTL);
|
||||
val &= ~DP_MODE_MASK;
|
||||
val |= DP_MODE_ENTER_A2;
|
||||
writel(val, tcphy->base + DP_MODE_CTL);
|
||||
ret = tcphy_dp_set_power_state(tcphy, PHY_DP_POWER_STATE_A2);
|
||||
if (ret) {
|
||||
dev_err(tcphy->dev, "failed to enter A2 power state\n");
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
if (tcphy->mode == MODE_DISCONNECT)
|
||||
tcphy_phy_deinit(tcphy);
|
||||
|
|
@ -1124,12 +1415,32 @@ static const struct phy_ops rockchip_dp_phy_ops = {
|
|||
};
|
||||
|
||||
static int typec_dp_phy_config(struct phy *phy, int link_rate,
|
||||
int lanes, u8 swing, u8 pre_emp)
|
||||
int lane_count, u8 swing, u8 pre_emp)
|
||||
{
|
||||
struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
|
||||
u8 i;
|
||||
int ret;
|
||||
|
||||
tcphy_cfg_dp_pll(tcphy, link_rate);
|
||||
dev_dbg(tcphy->dev, "link_rate=%d, lane_count=%d\n",
|
||||
link_rate, lane_count);
|
||||
dev_dbg(tcphy->dev, "voltage_swing=%d, pre_emphasis=%d\n",
|
||||
swing, pre_emp);
|
||||
|
||||
if (lane_count != tcphy->dp.lane_count) {
|
||||
ret = tcphy_dp_set_lane_count(tcphy, lane_count);
|
||||
if (ret) {
|
||||
dev_err(tcphy->dev, "failed to set lane count\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (link_rate != tcphy->dp.link_rate) {
|
||||
ret = tcphy_dp_set_link_rate(tcphy, link_rate);
|
||||
if (ret) {
|
||||
dev_err(tcphy->dev, "failed to set lane rate\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (tcphy->mode == MODE_DFP_DP) {
|
||||
for (i = 0; i < 4; i++)
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ struct rockchip_typec_phy {
|
|||
bool flip;
|
||||
u8 mode;
|
||||
struct phy_config config[3][4];
|
||||
struct {
|
||||
int link_rate;
|
||||
u8 lane_count;
|
||||
} dp;
|
||||
int (*typec_phy_config)(struct phy *phy, int link_rate,
|
||||
int lanes, u8 swing, u8 pre_emp);
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user