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KVM: x86/mmu: store shadow EFER.NX in the MMU role
Now that the MMU role is separate from the CPU role, it can be a truthful description of the format of the shadow pages. This includes whether the shadow pages use the NX bit; so force the efer_nx field of the MMU role when TDP is disabled, and remove the hardcoding it in the callers of reset_shadow_zero_bits_mask. In fact, the initialization of reserved SPTE bits can now be made common to shadow paging and shadow NPT; move it to shadow_mmu_init_context. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -4473,16 +4473,6 @@ static inline u64 reserved_hpa_bits(void)
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static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
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struct kvm_mmu *context)
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{
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/*
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* KVM uses NX when TDP is disabled to handle a variety of scenarios,
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* notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
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* to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
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* The iTLB multi-hit workaround can be toggled at any time, so assume
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* NX can be used by any non-nested shadow MMU to avoid having to reset
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* MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
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*/
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bool uses_nx = is_efer_nx(context) || !tdp_enabled;
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/* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
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bool is_amd = true;
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/* KVM doesn't use 2-level page tables for the shadow MMU. */
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@ -4494,7 +4484,8 @@ static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
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shadow_zero_check = &context->shadow_zero_check;
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__reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
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context->shadow_root_level, uses_nx,
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context->shadow_root_level,
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context->mmu_role.base.efer_nx,
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guest_can_use_gbpages(vcpu), is_pse, is_amd);
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if (!shadow_me_mask)
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@ -4858,6 +4849,16 @@ kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
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else
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role.base.level = PT64_ROOT_4LEVEL;
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/*
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* KVM forces EFER.NX=1 when TDP is disabled, reflect it in the MMU role.
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* KVM uses NX when TDP is disabled to handle a variety of scenarios,
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* notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
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* to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
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* The iTLB multi-hit workaround can be toggled at any time, so assume
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* NX can be used by any non-nested shadow MMU to avoid having to reset
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* MMU contexts.
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*/
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role.base.efer_nx = true;
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return role;
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}
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