github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-11-07 06:17:02 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

clk: qcom: gcc-sm8250: Use common clock controller probe data

Browse Source 
Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.

Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.

Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-29-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa 2026-09-24 15:06:41 +03:00 committed by Bjorn Andersson
parent 9100afaa49
commit 361b375a4b
1 changed files with 29 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
drivers/clk/qcom/gcc-sm8250.c
View File

@ -3603,6 +3603,15 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
};
static const u32 gcc_sm8250_critical_cbcrs[] = {
0x0b004, /* GCC_VIDEO_AHB_CLK */
0x0b008, /* GCC_CAMERA_AHB_CLK */
0x0b00c, /* GCC_DISP_AHB_CLK */
0x4818c, /* GCC_CPUSS_DVM_BUS_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x52000, /* GCC_SYS_NOC_CPUSS_AHB_CLK */
};
static const struct regmap_config gcc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -3611,6 +3620,24 @@ static const struct regmap_config gcc_sm8250_regmap_config = {
.fast_io = true,
};
static void gcc_sm8250_regs_configure(struct device *dev, struct regmap *regmap)
{
/*
* Disable the GPLL0 active input to NPU and GPU
* via MISC registers.
*/
regmap_set_bits(regmap, 0x4d110, 0x3);
regmap_set_bits(regmap, 0x71028, 0x3);
}
static const struct qcom_cc_driver_data gcc_sm8250_driver_data = {
.clk_cbcrs = gcc_sm8250_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sm8250_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
.clk_regs_configure = gcc_sm8250_regs_configure,
};
static const struct qcom_cc_desc gcc_sm8250_desc = {
.config = &gcc_sm8250_regmap_config,
.clks = gcc_sm8250_clocks,
@ -3619,6 +3646,7 @@ static const struct qcom_cc_desc gcc_sm8250_desc = {
.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
.gdscs = gcc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
.driver_data = &gcc_sm8250_driver_data,
};
static const struct of_device_id gcc_sm8250_match_table[] = {
@ -3629,34 +3657,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8250_match_table);
static int gcc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm8250_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to NPU and GPU
* via MISC registers.
*/
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */
qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8250_desc, regmap);
return qcom_cc_probe(pdev, &gcc_sm8250_desc);
}
static struct platform_driver gcc_sm8250_driver = {