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drm/amd/display: bypass post csc for additional color spaces in dcn42

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[Why]
This aligns dcn42 with:
"drm/amd/display: bypass post csc for additional color spaces in dal"

[How]
Apply the same post csc bypass logic to dcn42 dpp using the
helper function.

Signed-off-by: Roman Li <roman.li@amd.com>
Acked-by: Chenyu Chen <chen-yu.chen@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li 2026-04-13 17:32:55 -04:00 committed by Alex Deucher
parent 4aebe73f44
commit 35e86e6a54
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
View File

@ -269,10 +269,10 @@ static void dpp42_dpp_setup(
tbl_entry.color_space = input_color_space;
if (color_space >= COLOR_SPACE_YCBCR601)
select = INPUT_CSC_SELECT_ICSC;
else
if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
select = INPUT_CSC_SELECT_BYPASS;
else
select = INPUT_CSC_SELECT_ICSC;
dpp3_program_post_csc(dpp_base, color_space, select,
&tbl_entry);