github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-28 17:13:52 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree

Browse Source 
The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
the necessary dts nodes and properties for this.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Chris Packham 2021-12-06 11:56:18 +13:00 committed by Gregory CLEMENT
parent 1f1cb308ab
commit 35d544a273
1 changed files with 130 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

130
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
View File

@ -73,6 +73,17 @@ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
enable-active-high;
regulator-always-on;
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
los-gpio = <&expander0 15 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
status = "okay";
};
};
&uart0 {
@ -195,6 +206,125 @@ &cp0_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
switch6: switch0@6 {
/* Actual device is MV88E6393X */
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "p1";
phy-handle = <&switch0phy1>;
};
port@2 {
reg = <2>;
label = "p2";
phy-handle = <&switch0phy2>;
};
port@3 {
reg = <3>;
label = "p3";
phy-handle = <&switch0phy3>;
};
port@4 {
reg = <4>;
label = "p4";
phy-handle = <&switch0phy4>;
};
port@5 {
reg = <5>;
label = "p5";
phy-handle = <&switch0phy5>;
};
port@6 {
reg = <6>;
label = "p6";
phy-handle = <&switch0phy6>;
};
port@7 {
reg = <7>;
label = "p7";
phy-handle = <&switch0phy7>;
};
port@8 {
reg = <8>;
label = "p8";
phy-handle = <&switch0phy8>;
};
port@9 {
reg = <9>;
label = "p9";
phy-mode = "10gbase-r";
sfp = <&sfp>;
managed = "in-band-status";
};
port@a {
reg = <10>;
label = "cpu";
ethernet = <&cp0_eth0>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
};
};
&cp0_xmdio {