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Merge branch 'for-next/mpam' into for-next/core
* for-next/mpam: arm_mpam: Update architecture version check for MPAM MSC arm64: cpufeature: Add support for the MPAM v0.1 architecture version
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commit
3594da9b7a
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@ -620,6 +620,13 @@ static inline bool id_aa64pfr0_mpam(u64 pfr0)
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return val > 0;
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}
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static inline bool id_aa64pfr1_mpamfrac(u64 pfr1)
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{
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u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MPAM_frac_SHIFT);
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return val > 0;
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}
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static inline bool id_aa64pfr1_mte(u64 pfr1)
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{
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u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
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@ -510,7 +510,9 @@
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#endif
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.macro finalise_el2_state
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check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2
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check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lmpam_minor_\@, x1, x2
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.Lmpam_minor_\@:
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check_override id_aa64pfr1, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2
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.Linit_mpam_\@:
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mov x0, #MPAM2_EL2_EnMPAMSM_MASK
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@ -1167,6 +1167,14 @@ static __init void detect_system_supports_pseudo_nmi(void)
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static inline void detect_system_supports_pseudo_nmi(void) { }
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#endif
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static bool detect_ftr_has_mpam(void)
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{
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u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
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u64 pfr1 = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
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return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1);
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}
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void __init init_cpu_features(struct cpuinfo_arm64 *info)
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{
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/* Before we start using the tables, make sure it is sorted */
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@ -1214,7 +1222,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
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cpacr_restore(cpacr);
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}
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if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
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if (detect_ftr_has_mpam()) {
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info->reg_mpamidr = read_cpuid(MPAMIDR_EL1);
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init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr);
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}
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@ -1470,7 +1478,7 @@ void update_cpu_features(int cpu,
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cpacr_restore(cpacr);
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}
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if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
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if (detect_ftr_has_mpam()) {
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info->reg_mpamidr = read_cpuid(MPAMIDR_EL1);
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taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu,
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info->reg_mpamidr, boot->reg_mpamidr);
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@ -2489,7 +2497,7 @@ cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
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static bool
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test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope)
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{
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if (!has_cpuid_feature(entry, scope))
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if (!detect_ftr_has_mpam())
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return false;
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/* Check firmware actually enabled MPAM on this cpu. */
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@ -3096,7 +3104,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.capability = ARM64_MPAM,
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.matches = test_has_mpam,
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.cpu_enable = cpu_enable_mpam,
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ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1)
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},
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{
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.desc = "Memory Partitioning And Monitoring Virtualisation",
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@ -218,6 +218,24 @@ static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u32 val
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#define mpam_write_monsel_reg(msc, reg, val) _mpam_write_monsel_reg(msc, MSMON_##reg, val)
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static bool mpam_msc_check_aidr(struct mpam_msc *msc)
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{
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u32 aidr = __mpam_read_reg(msc, MPAMF_AIDR);
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u32 major = FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr);
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u32 minor = FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr);
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/*
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* v0.0 and >v2.x aren't supported, but anything else should be backward
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* compatible to v0.1 or v1.0.
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*/
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if (!major && !minor)
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return false;
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if (major > 1)
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return false;
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return true;
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}
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static u64 mpam_msc_read_idr(struct mpam_msc *msc)
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{
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u64 idr_high = 0, idr_low;
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@ -945,9 +963,8 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
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lockdep_assert_held(&msc->probe_lock);
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idr = __mpam_read_reg(msc, MPAMF_AIDR);
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if ((idr & MPAMF_AIDR_ARCH_MAJOR_REV) != MPAM_ARCHITECTURE_V1) {
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dev_err_once(dev, "MSC does not match MPAM architecture v1.x\n");
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if (!mpam_msc_check_aidr(msc)) {
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dev_err_once(dev, "MSC does not match architecture v1.x\n");
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return -EIO;
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}
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