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drm/amdgpu/ttm: Add New AMDGPU_PL_MMIO_REMAP Placement
Introduce a kernel-internal TTM placement type AMDGPU_PL_MMIO_REMAP
for the HDP flush MMIO remap page
Plumbing added:
- amdgpu_res_cursor.{first,next}: treat MMIO_REMAP like DOORBELL
- amdgpu_ttm_io_mem_reserve(): return BAR bus address + offset
for MMIO_REMAP, mark as uncached I/O
- amdgpu_ttm_io_mem_pfn(): PFN from register BAR
- amdgpu_res_cpu_visible(): visible to CPU
- amdgpu_evict_flags()/amdgpu_bo_move(): non-migratable
- amdgpu_ttm_tt_pde_flags(): map as SYSTEM
- amdgpu_bo_mem_stats_placement(): report AMDGPU_PL_MMIO_REMAP
- amdgpu_fdinfo: print “mmioremap” bucket label
Cc: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -34,7 +34,8 @@
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#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
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#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
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#define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4)
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#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 5)
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#define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5)
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#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
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#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
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#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
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