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TI K3 device tree updates for v6.15
Generic Fixups/Cleanups: SoC Specific features and Fixes: AM62Ax: Enable MCU domain pinctrl node J784S4/J742S4: GICD reg size fixes Serdes lane ctrl reg mux mask fix AM62P/J722s: Wakeup UART0 sysc updates for system wakeup pinctrl node fixes drop pinctrl-single,gpio-ranges BCDMA CSI-RX support Audio REFCLKx output support Board Specific: J784S4: EVM: Cleanup duplicate gpio-hogs J722S: TypeC port mux selection fix AM62Ax SK: boot-phase tag to support USB bootmode RTC support Aliases for wakeup and MCU serial UARTs AM62P SK: boot-phase tag to support USB bootmode USB wakeup support Aliases for wakeup and MCU serial UARTs AM62: verdin-dahila: microphone support SK: Aliases for wakeup and MCU serial UARTs BeaglePlay: reserved CMA region for Multimedia applications J721e: SK/EVM: boot-phase tags for Serdes for DFU boot Phytech board updates: Boot-phase tag updates for AM64/AM62/AM62A boards DTS coding style cleanups RTOS IPC reserved-memory additions DT overlay for X27 Connectors on AM64 SOMs J721S2 SOM: Add flash partitions -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmfRDioQHHZpZ25lc2hy QHRpLmNvbQAKCRDERh5FfJEW4w/fB/92ly/Q276g9OKSXOPQXvOS/L/7CJ8wQcxs y+kmtwSKUjSMeliWVR+wNX9jsi4JYvC7Eji4aJxNitRxQdBy0o4TYc2Ucrrfr2Xl 7AH7H9cg+aOAvt3tMbLf6T9CKaJXjiKuFIw6/QtDFx7KAF632KC5G86tiFKJ3X+N 3G3AxChZbv9nLMUVs3Av/h12Ok8WqScgikDbbGCu9N5h6q1lQKDClGXlrKBLeXOk tY5bMX48HaIoNGVH/YV9wDiFoCrY/t8f7AUS0ob79eE6tkpBuG5krmhBnNevIVpC ijL0chfrV/bfLoOhZvMjK4/JmtG8iZl+TDQnrctrg6Ujh1SUwT8m =44GG -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfUrmQACgkQYKtH/8kJ UicQmBAAv4e1To6a/1qXnEI9q2okNJaRCdi6uJZc0r1xVOaD+3E+Q3SmimVpDMaM EJ7XlHAyY2Y+EtSjbsgAPTL0Emk6dkssJUqieyXAw/Gf0eneE/8rmY+2ydm/J7ul 7bPBopmKkkACxpqNl63EKM3PqG56U5ZQ2fBTlXgjLaEhvB+tuEgVWmuXcJxZJLBZ U1K7AvH2Gzoy0J/xzRQSGN9VnloWYKasbfgpdufFsr0O2hfm0Olbg6k53OZaHuh5 mL8BY40GnH1m2GZrkgGjNcWkt3GIFTbwOg5UJsqRBQ0QzgymSoRuCxjgt6Opx//U /J+qhCL43dDGoQh08wd5zgEiNLBGLb2kO5N3n/paeHLtFVuOB4idbpse4qL7dCr0 7U+MkL0TdD9ZpOGN+K2DuuVm3VW3gahXpa9DUTpFJRNEncKRmb7//I4xalkjoyh+ ubRxWQV1jwNoUTL0kvpSoojMtVNdLpJi4IAbQTzVzrFSkr/1lZZGwyiN5MrZVU+C VdpTWL1wr0aNhpBxIzK+RMwtTTrZluqiEgUSLb2/J2c6Ke/W/uro16LjqMu7dkXe GJdG2ljV8ZH6L9MqW39Qwnx5xhWjzBjsmOt42AsdzRDCxjlg5YdEECrGobkVk+rS eiwp4yW9YA1GQnqj4J6GbwNMzvdSXYAq3mKTJ+aIDZTJ/gDCqhk= =11gj -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.15 Generic Fixups/Cleanups: SoC Specific features and Fixes: AM62Ax: Enable MCU domain pinctrl node J784S4/J742S4: GICD reg size fixes Serdes lane ctrl reg mux mask fix AM62P/J722s: Wakeup UART0 sysc updates for system wakeup pinctrl node fixes drop pinctrl-single,gpio-ranges BCDMA CSI-RX support Audio REFCLKx output support Board Specific: J784S4: EVM: Cleanup duplicate gpio-hogs J722S: TypeC port mux selection fix AM62Ax SK: boot-phase tag to support USB bootmode RTC support Aliases for wakeup and MCU serial UARTs AM62P SK: boot-phase tag to support USB bootmode USB wakeup support Aliases for wakeup and MCU serial UARTs AM62: verdin-dahila: microphone support SK: Aliases for wakeup and MCU serial UARTs BeaglePlay: reserved CMA region for Multimedia applications J721e: SK/EVM: boot-phase tags for Serdes for DFU boot Phytech board updates: Boot-phase tag updates for AM64/AM62/AM62A boards DTS coding style cleanups RTOS IPC reserved-memory additions DT overlay for X27 Connectors on AM64 SOMs J721S2 SOM: Add flash partitions * tag 'ti-k3-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (32 commits) arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags arm64: dts: ti: k3-j722s-evm: Add camera peripherals arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides arm64: dts: ti: k3-j722s: fix pinctrl settings arm64: dts: ti: k3-am62p: fix pinctrl settings arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory arm64: dts: ti: k3-am62p5-sk: Add serial alias arm64: dts: ti: k3-am62a7-sk: Add serial alias arm64: dts: ti: k3-am62x-sk-common: Add serial aliases arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA ... Link: https://lore.kernel.org/r/5d612c0e-4cd4-469a-9856-dd4552d74412@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
35759662ef
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@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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@ -185,6 +186,8 @@ k3-am642-phyboard-electra-gpio-fan-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo
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k3-am642-phyboard-electra-pcie-usb2-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo
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k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo
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k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
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k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
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@ -29,6 +29,7 @@ aliases {
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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bootph-all;
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};
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reserved_memory: reserved-memory {
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@ -36,15 +37,21 @@ reserved_memory: reserved-memory {
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#size-cells = <2>;
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ranges;
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ramoops@9ca00000 {
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ramoops@9c700000 {
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compatible = "ramoops";
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reg = <0x00 0x9ca00000 0x00 0x00100000>;
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reg = <0x00 0x9c700000 0x00 0x00100000>;
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record-size = <0x8000>;
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console-size = <0x8000>;
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ftrace-size = <0x00>;
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pmsg-size = <0x8000>;
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};
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rtos_ipc_memory_region: ipc-memories@9c800000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x9c800000 0x00 0x00300000>;
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no-map;
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};
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mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x9cb00000 0x00 0x100000>;
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@ -131,6 +138,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
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AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
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AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
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>;
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bootph-all;
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};
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main_mdio1_pins_default: main-mdio1-default-pins {
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@ -138,6 +146,7 @@ main_mdio1_pins_default: main-mdio1-default-pins {
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AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
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AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
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>;
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bootph-all;
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};
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main_mmc0_pins_default: main-mmc0-default-pins {
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@ -153,6 +162,7 @@ AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
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AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
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AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
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>;
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bootph-all;
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};
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main_rgmii1_pins_default: main-rgmii1-default-pins {
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@ -170,6 +180,7 @@ AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
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AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
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AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
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>;
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bootph-all;
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};
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ospi0_pins_default: ospi0-default-pins {
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@ -186,6 +197,7 @@ AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
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AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
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AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
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>;
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bootph-all;
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};
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pmic_irq_pins_default: pmic-irq-default-pins {
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@ -210,6 +222,7 @@ &cpsw3g {
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy1>;
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bootph-all;
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};
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&cpsw3g_mdio {
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@ -220,6 +233,7 @@ &cpsw3g_mdio {
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cpsw3g_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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bootph-all;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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@ -232,10 +246,15 @@ mbox_m4_0: mbox-m4-0 {
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};
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};
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&main_pktdma {
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bootph-all;
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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bootph-all;
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status = "okay";
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pmic@30 {
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@ -355,6 +374,7 @@ serial_flash: flash@0 {
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <0>;
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bootph-all;
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};
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};
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@ -363,5 +383,6 @@ &sdhci0 {
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pinctrl-0 = <&main_mmc0_pins_default>;
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disable-wp;
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non-removable;
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bootph-all;
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status = "okay";
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};
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@ -28,10 +28,10 @@ sound {
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"Headphone Jack", "HPOUTR",
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"IN2L", "Line In Jack",
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"IN2R", "Line In Jack",
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"Headphone Jack", "MICBIAS",
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"IN1L", "Headphone Jack";
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"Microphone Jack", "MICBIAS",
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"IN1L", "Microphone Jack";
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simple-audio-card,widgets =
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"Microphone", "Headphone Jack",
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Line", "Line In Jack";
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@ -65,6 +65,14 @@ ramoops: ramoops@9ca00000 {
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pmsg-size = <0x8000>;
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};
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/* global cma region */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x00 0x8000000>;
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linux,cma-default;
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};
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secure_tfa_ddr: tfa@9e780000 {
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reg = <0x00 0x9e780000 0x00 0x80000>;
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no-map;
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@ -12,7 +12,6 @@ mcu_pmx0: pinctrl@4084000 {
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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status = "disabled";
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};
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mcu_esm: esm@4100000 {
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@ -42,6 +42,7 @@ memory@80000000 {
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device_type = "memory";
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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bootph-all;
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};
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reserved-memory {
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@ -99,6 +100,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
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AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */
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AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */
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>;
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bootph-all;
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};
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main_mdio1_pins_default: main-mdio1-default-pins {
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@ -106,6 +108,7 @@ main_mdio1_pins_default: main-mdio1-default-pins {
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AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
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AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
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>;
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bootph-all;
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};
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main_mmc0_pins_default: main-mmc0-default-pins {
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@ -121,6 +124,7 @@ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
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AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
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AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
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>;
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bootph-all;
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};
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main_rgmii1_pins_default: main-rgmii1-default-pins {
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@ -138,6 +142,7 @@ AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */
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AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */
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AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */
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>;
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bootph-all;
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};
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ospi0_pins_default: ospi0-default-pins {
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@ -155,6 +160,7 @@ AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
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AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
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AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
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>;
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bootph-all;
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};
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pmic_irq_pins_default: pmic-irq-default-pins {
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@ -165,14 +171,15 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
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};
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&cpsw3g {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_rgmii1_pins_default>;
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status = "okay";
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy1>;
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bootph-all;
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};
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&cpsw3g_mdio {
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@ -182,6 +189,7 @@ &cpsw3g_mdio {
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cpsw3g_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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bootph-all;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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@ -196,6 +204,7 @@ &main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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bootph-all;
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status = "okay";
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pmic@30 {
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@ -215,8 +224,8 @@ pmic@30 {
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interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,power-button;
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||||
system-power-controller;
|
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ti,power-button;
|
||||
|
||||
regulators {
|
||||
vdd_3v3: buck1 {
|
||||
|
|
@ -302,6 +311,10 @@ &main_gpio_intr {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&main_pktdma {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
|
@ -318,6 +331,7 @@ serial_flash: flash@0 {
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -326,5 +340,6 @@ &sdhci0 {
|
|||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,10 +18,13 @@ / {
|
|||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
rtc0 = &wkup_rtc0;
|
||||
rtc1 = &tps659312;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -655,6 +658,7 @@ &usbss0 {
|
|||
};
|
||||
|
||||
&usb0 {
|
||||
bootph-all;
|
||||
usb-role-switch;
|
||||
|
||||
port {
|
||||
|
|
|
|||
|
|
@ -12,15 +12,7 @@ mcu_pmx0: pinctrl@4084000 {
|
|||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
pinctrl-single,gpio-range =
|
||||
<&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
|
||||
bootph-all;
|
||||
|
||||
mcu_pmx_range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_esm: esm@4100000 {
|
||||
|
|
|
|||
|
|
@ -2,9 +2,11 @@
|
|||
/*
|
||||
* Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
|
||||
*
|
||||
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/bus/ti-sysc.h>
|
||||
|
||||
&cbass_wakeup {
|
||||
wkup_conf: bus@43000000 {
|
||||
compatible = "simple-bus";
|
||||
|
|
@ -41,14 +43,34 @@ usb1_phy_ctrl: syscon@4018 {
|
|||
};
|
||||
};
|
||||
|
||||
wkup_uart0: serial@2b300000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x2b300000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
target-module@2b300050 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0 0x2b300050 0 0x4>,
|
||||
<0 0x2b300054 0 0x4>,
|
||||
<0 0x2b300058 0 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,syss-mask = <1>;
|
||||
ti,no-reset-on-init;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fclk";
|
||||
status = "disabled";
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x2b300000 0x100000>;
|
||||
|
||||
wkup_uart0: serial@0 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@2b200000 {
|
||||
|
|
|
|||
|
|
@ -42,17 +42,23 @@ &inta_main_dmss {
|
|||
ti,interrupt-ranges = <5 69 35>;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pinctrl-single,gpio-range =
|
||||
<&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
|
||||
&main_conf {
|
||||
audio_refclk0: clock-controller@82e0 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e0 0x4>;
|
||||
clocks = <&k3_clks 157 0>;
|
||||
assigned-clocks = <&k3_clks 157 0>;
|
||||
assigned-clock-parents = <&k3_clks 157 16>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
main_pmx0_range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
audio_refclk1: clock-controller@82e4 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e4 0x4>;
|
||||
clocks = <&k3_clks 157 18>;
|
||||
assigned-clocks = <&k3_clks 157 18>;
|
||||
assigned-clock-parents = <&k3_clks 157 34>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ / {
|
|||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
mmc0 = &sdhci0;
|
||||
|
|
@ -310,7 +311,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */
|
|||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */
|
||||
AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -519,6 +520,7 @@ &usbss1 {
|
|||
};
|
||||
|
||||
&usb0 {
|
||||
bootph-all;
|
||||
usb-role-switch;
|
||||
|
||||
port {
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ vcc_3v3_mmc: regulator-vcc-3v3-mmc {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vcc_3v3_sw: regulator-vcc-3v3-sw {
|
||||
|
|
@ -233,6 +234,7 @@ AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
|
|||
AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
|
||||
AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_rgmii2_pins_default: main-rgmii2-default-pins {
|
||||
|
|
@ -257,6 +259,7 @@ main_uart0_pins_default: main-uart0-default-pins {
|
|||
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
|
||||
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
|
|
@ -266,6 +269,7 @@ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
|
|||
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
|
||||
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
|
||||
>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
|
|
@ -430,12 +434,14 @@ &main_mcan0 {
|
|||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
bootph-pre-ram;
|
||||
/* Main UART1 may be used by TIFS firmware */
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -467,11 +473,13 @@ &sdhci1 {
|
|||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -482,6 +490,7 @@ &usbss1 {
|
|||
|
||||
&usb0 {
|
||||
usb-role-switch;
|
||||
bootph-all;
|
||||
|
||||
port {
|
||||
typec_hs: endpoint {
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ aliases {
|
|||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
@ -99,6 +100,12 @@ mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
|||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
@ -132,6 +139,7 @@ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
|||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
|
||||
|
|
@ -150,6 +158,7 @@ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
|
|||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
eeprom_wp_pins_default: eeprom-wp-default-pins {
|
||||
|
|
@ -169,6 +178,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
|
|||
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
|
|
@ -185,6 +195,7 @@ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
|||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
rtc_pins_default: rtc-defaults-pins {
|
||||
|
|
@ -201,26 +212,29 @@ &cpsw3g {
|
|||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpsw_mdio_pins_default>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <1000>;
|
||||
reset-deassert-us = <1000>;
|
||||
bootph-all;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -262,10 +276,11 @@ mbox_m4_0: mbox-m4-0 {
|
|||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
|
|
@ -330,6 +345,10 @@ vdda_1v8: ldo1 {
|
|||
};
|
||||
};
|
||||
|
||||
&main_pktdma {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
|
|
@ -362,9 +381,9 @@ &mcu_m4fss {
|
|||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
status = "okay";
|
||||
|
||||
serial_flash: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
@ -377,15 +396,17 @@ serial_flash: flash@0 {
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
keep-power-in-suspend;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
|
|
|
|||
|
|
@ -171,6 +171,7 @@ vcc_3v3_mmc: regulator-sd {
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -275,6 +276,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
|
|||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_spi0_pins_default: main-spi0-default-pins {
|
||||
|
|
@ -291,6 +293,7 @@ main_uart0_pins_default: main-uart0-default-pins {
|
|||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
|
|
@ -349,10 +352,10 @@ &i2c_som_rtc {
|
|||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
|
|
@ -382,25 +385,25 @@ led-5 {
|
|||
};
|
||||
|
||||
&main_mcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&can_tc1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_mcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan1_pins_default>;
|
||||
phys = <&can_tc2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
status = "okay";
|
||||
|
||||
tpm@1 {
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
|
|
@ -410,25 +413,27 @@ tpm@1 {
|
|||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vcc_3v3_mmc>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
|
||||
* Authors:
|
||||
* Wadim Egorov <w.egorov@phytec.de>
|
||||
* Daniel Schultz <d.schultz@phytec.de>
|
||||
*
|
||||
* GPIO, SPI and UART examples for the X27 expansion connector.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&{/} {
|
||||
aliases {
|
||||
serial5 = "/bus@f4000/serial@2830000";
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_spi1_pins_default: main-spi1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
|
||||
AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
|
||||
AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */
|
||||
AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart3_pins_default: main-uart3-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
|
||||
AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_gpio1_exp_header_gpio_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi1_pins_default>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart3_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -540,6 +540,7 @@ serdes3_usb_link: phy@0 {
|
|||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1040,6 +1040,7 @@ serdes3_usb_link: phy@0 {
|
|||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -448,6 +448,47 @@ flash@0 {
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6c0000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -263,6 +263,13 @@ J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
main_i2c2_pins_default: main-i2c2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */
|
||||
J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
|
||||
|
|
@ -590,7 +597,7 @@ exp1: gpio@23 {
|
|||
p05-hog {
|
||||
/* P05 - USB2.0_MUX_SEL */
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
|
|
@ -631,6 +638,27 @@ tlv320aic3106: audio-codec@1b {
|
|||
};
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c2_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pca9543_0: i2c-mux@70 {
|
||||
compatible = "nxp,pca9543";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
pca9543_1: i2c-mux@71 {
|
||||
compatible = "nxp,pca9543";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x71>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
|
|
|||
|
|
@ -154,6 +154,189 @@ usb1: usb@31200000 {
|
|||
};
|
||||
};
|
||||
|
||||
ti_csi2rx1: ticsi2rx@30122000 {
|
||||
compatible = "ti,j721e-csi2rx-shim";
|
||||
reg = <0x00 0x30122000 0x00 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dmas = <&main_bcdma_csi 0 0x5100 0>;
|
||||
dma-names = "rx0";
|
||||
power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
cdns_csi2rx1: csi-bridge@30121000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30121000 0x00 0x1000>;
|
||||
clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>,
|
||||
<&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
|
||||
phys = <&dphy1>;
|
||||
phy-names = "dphy";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi1_port0: port@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi1_port1: port@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi1_port2: port@2 {
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi1_port3: port@3 {
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi1_port4: port@4 {
|
||||
reg = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ti_csi2rx2: ticsi2rx@30142000 {
|
||||
compatible = "ti,j721e-csi2rx-shim";
|
||||
reg = <0x00 0x30142000 0x00 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
|
||||
dmas = <&main_bcdma_csi 0 0x5200 0>;
|
||||
dma-names = "rx0";
|
||||
status = "disabled";
|
||||
|
||||
cdns_csi2rx2: csi-bridge@30141000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30141000 0x00 0x1000>;
|
||||
clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>,
|
||||
<&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
|
||||
phys = <&dphy2>;
|
||||
phy-names = "dphy";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_port0: port@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi2_port1: port@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi2_port2: port@2 {
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi2_port3: port@3 {
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi2_port4: port@4 {
|
||||
reg = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ti_csi2rx3: ticsi2rx@30162000 {
|
||||
compatible = "ti,j721e-csi2rx-shim";
|
||||
reg = <0x00 0x30162000 0x00 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dmas = <&main_bcdma_csi 0 0x5300 0>;
|
||||
dma-names = "rx0";
|
||||
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
cdns_csi2rx3: csi-bridge@30161000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30161000 0x00 0x1000>;
|
||||
clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>,
|
||||
<&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
|
||||
phys = <&dphy3>;
|
||||
phy-names = "dphy";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi3_port0: port@0 {
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi3_port1: port@1 {
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi3_port2: port@2 {
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi3_port3: port@3 {
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi3_port4: port@4 {
|
||||
reg = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dphy1: phy@30130000 {
|
||||
compatible = "cdns,dphy-rx";
|
||||
reg = <0x00 0x30130000 0x00 0x1100>;
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dphy2: phy@30150000 {
|
||||
compatible = "cdns,dphy-rx";
|
||||
reg = <0x00 0x30150000 0x00 0x1100>;
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dphy3: phy@30170000 {
|
||||
compatible = "cdns,dphy-rx";
|
||||
reg = <0x00 0x30170000 0x00 0x1100>;
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss0: r5fss@78400000 {
|
||||
compatible = "ti,am62-r5fss";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -204,6 +387,16 @@ c7x_1: dsp@7e200000 {
|
|||
};
|
||||
};
|
||||
|
||||
&main_bcdma_csi {
|
||||
compatible = "ti,j722s-dmss-bcdma-csi";
|
||||
reg = <0x00 0x4e230000 0x00 0x100>,
|
||||
<0x00 0x4e180000 0x00 0x20000>,
|
||||
<0x00 0x4e300000 0x00 0x10000>,
|
||||
<0x00 0x4e100000 0x00 0x80000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
|
||||
ti,sci-rm-range-tchan = <0x22>;
|
||||
};
|
||||
|
||||
/* MCU domain overrides */
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
|
|
@ -251,21 +444,6 @@ &inta_main_dmss {
|
|||
ti,interrupt-ranges = <7 71 21>;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pinctrl-single,gpio-range =
|
||||
<&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
|
||||
<&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
|
||||
|
||||
main_pmx0_range: gpio-range {
|
||||
#pinctrl-single,gpio-range-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
|
||||
<&main_pmx0 70 72 17>;
|
||||
|
|
|
|||
|
|
@ -102,13 +102,6 @@ qsgmii-line-hog {
|
|||
gpios = <16 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
};
|
||||
|
||||
/* Toggle MUX2 for MDIO lines */
|
||||
mux-sel-hog {
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
|
|||
|
|
@ -84,7 +84,9 @@ serdes_ln_ctrl: mux-controller@4080 {
|
|||
<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
|
||||
<0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
|
||||
<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
|
||||
<0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */
|
||||
<0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */
|
||||
<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
|
||||
<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
|
||||
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
|
||||
<J784S4_SERDES0_LANE1_PCIE1_LANE1>,
|
||||
<J784S4_SERDES0_LANE2_IP3_UNUSED>,
|
||||
|
|
@ -193,7 +195,7 @@ gic500: interrupt-controller@1800000 {
|
|||
ranges;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
|
||||
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||
<0x00 0x01900000 0x00 0x100000>, /* GICR */
|
||||
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
|
||||
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user